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Course: FPGA computing systems: Background knowledge and introductory materials. Click here to go back.
- Course Introduction
- Reconfiguration in Everyday Life
- The Needs for Adaptation: an overview
- FPGA and reconfiguration: a 1st definition
- Runtime management
- Programmable System-on-Chip
- Programmable System-on-Multiple Chip
- Reconfigurable Computing: a 1st definition
- Reconfigurable Computing: HW vs SW
- On how to improve the Reconfigurable computing performance via CAD improvements
- FPGA-Based Reconfigurable Computing
- System design space exploration and rationale behind partial reconfiguration
- Getting Familiar with FPGAs
- FPGA Basic Block: CLBs and IOBs
- FPGA Basic Block: Interconnections
- FPGA Configuration: an overview
- More Details on How To Configure and FPGA: the bitstream files
- Bitstream Composition
- Configuration Registers
- How to handle the complexity of an FPGA-based system
- 4 inputs - 1 output OR LUT configuration example
- From the LUT to the CLB configuration example
- A simplified FPGA and its configuration settings
- An Example on how to implement a circuit on a simplified FPGA
- An Example on how to implement a circuit on a simplified FPGA: bitstram generation phase - CLBs
- An Example on how to implement a circuit on a simplified FPGA: bitstram generation phase - SBs and routing
- A Common Vocabulary
- The 5 W's
- Reconfigurable Computing as an Exstension of HW/SW Codesing
- A Classification of SoC Reconfigurations
- A Classification of SoMC Reconfigurations
- Scenarios where Partial Reconfiguration can be effective
- How to use FPGA Reconfiguration to face area issues
- How to deal with the Reconfiguration runtime overhead
- Recurring modules to reuse them to reduce the Reconfiguration time
- Partial Reconfiguration to reduce the Reconfiguration runtime overhead
- Runtime management to explore alternative implementations
- Bitstreams relocation
- Bitstreams relocation and virtual homogeneity
- Xilnx Design Flows through years
- Partial Reconfiguration Design Flows
- Xilinx Difference Based Partial Reconfiguration
- Xilinx Module Based Partial Reconfiguration
- Xilinx Partial Reconfiguration (PR) Flow
- Moudle Based vs Partial Reconfiguration Design Flows
- Rationale behind DRESD and the work done by the Politecnico di Milano
- From DRESD to CHANGE and ASAP, two new research initiatives from the Politecnico di Milano
- CAOS: from embedded to heterogeneous distributed FPGA-based computing systems
- Towards distributed FPGA-based systems