In our examples so far, we've been looking at code and threads running on a single processor. But in many systems, it's useful to be able to use the exclusive access instructions to synchronize access to data that's shared between multiple processors. The concept of exclusive monitors on load and store exclusives is available in all three profiles of the ARM architecture, A, R, and M. The same concept can even be used to share memory and synchronized accesses between different types of processors. The other thing we've not really talked about yet is where the monitor is implemented. The ARM architecture defines two different types of monitor, a local monitor and a global monitor. They both implement a version of the state machine we saw earlier. The local monitor is, as the name suggests, used for accesses which are local to a particular processor, and actually is implemented usually within the processor itself. The global monitor is used to synchronize accesses to globally visible data, that is data which is visible to more than one processor. When we're trying to synchronize accesses between two processors, both types of monitor are used. The local monitor on the processors are checked first, if they pass, then we'll also go on to check the global monitor. In certain situations though, it's not necessary to check the global monitor, for instance, if the memory is only shared between threads or processors on a single car, so we can use the memory attributes to determine which monitors we need to check. We'll discuss memory types, and particular shareability in another session. The shareability memory attribute is the one we use to determine which monitor to use. The local monitor is always used no matter what the shareability attributes of the memory is. The global monitor is only ever used when the memory has the shareability attributes. Here we can see two regions of memory, one which is non-shared, and one which is shared. Remember, this is the memory attributes shared. When we access this non-shared region, only the local monitor is checked, when we try and access the shared region, the local monitor is checked first, if the local monitor passes, then the access can be sent out onto the memory bus. Depending on which bus technology we use, the exclusive access is signaled in a slightly different way, but both AHB and AXI, the two types of bus infrastructure you're likely to see with Cortex and processors have the ability to signal and transport exclusive memory accesses. That exclusive access is now signaled on downstream in the memory system until it reaches a global monitor. The global monitor is very similar to the local monitor but it's implemented somewhere else in the memory system, not in the processor. Typically, it's either implemented in the busing to interconnect itself or in the RAM controller. This global monitor will also maintain an exclusive access state machine. For the STREX exclusive to succeed, this also has to be in the exclusive state. We've seen that which monetary is used depends on the shareability attribute of the memory region. For processors with an MPU, the shareability is just an attribute of the MPU region, actually configured in the MPU region base address register. If our processor doesn't have an MPU, or the MPU isn't currently being used, then we fall back to using a default memory map, which assigns default memory types to all regions of memory. In the default memory map, there are a number of regions defined as normal memory, but all of these have the non-shareable attributes, so that means they will not use the global monitor. Some implementations, such as M33 and M23 have an implementation specific feature, which allows them to force all non-shareable memory accesses to also use the global monitor. This is set by configuring the Auxiliary Control Register. If you're Cortex-M33 or M23 uses the TrustZone security extension, then the Auxiliary Control Register is also banked by security state. You may have different configurations for secure and non-secure code.
