Hello, everyone. My name is Yang Song, and I'm an Applications Engineer working at Arm. Today, we'll be discussing a very important topic to the Armv8-M Mainline Architecture, the memory model. At the end of this module, you should be able to list the different partitions of the Armv8-M Mainline address space and differentiate the Arm Architecture memory types and why they're used for certain partitions of the address space. You'll be able to identify the different memory attributes and their effects on loads and stores, and characterize the effects of Endianness on the Armv8-M processors. You will also be able to recognize different Barrier instructions and describe when and why they are used. Let's first discuss the memory address space. The Armv8-M is a memory-mapped architecture, in that it contains up to four gigabytes of physical address space. The address space is a shared address space for both physical memory and processor control and status registers. The memory is divided into 8 times 512 megabytes segments or partitions. Starting at x0000, it is the code section followed by 512 megabytes of SRAM, peripheral, two RAM regions, two device regions, and one system region. The system region contains a processor control and status registers. As we saw on the previous page, the Armv8-M memory map contains eight different regions. The eight different regions are defined with their own intended usages. The code section is memory to hold instructions. The SRAM, it's intended for fast SRAM memory usually some type of on-chip RAM. The next two RAM regions are typically reserved for off-chip RAM. Then you also have the peripheral region, which should contain peripheral memory space that are on-chip and they have two device regions that are intended for peripheral memory space, but for off-chip peripherals. The system, of course, contains the memory map registers. As you can see on this page, the dotted line dividing the top section and the bottom section determines whether the code execution is allowed. Code execution is only allowed in the code SRAM and RAM regions, and code execution is not allowed or the eXecute Never attribute is set for the peripheral to two device regions and the system memory region. Let's take a look at the system segment of memory first. This segment is used for control and configuration of the processor. The system region contains memory-mapped registers that control resources to the CPU, like the NVIC, the Nested Vector Interrupt Controller, the System Timer, and Debug registers. Technically, the top of memory, or the top portion of the system memory segment, the top 511 megabytes can be used for adding additional implementation-defined system space. If we look to the right side, we see a portion that is designated for the VENDOR_SYS. This area can be used by the SoC designers to write any pertinent information about their SoC. There's a segment that's reserved, meaning that no information should be left there. Then most of the control configuration registers are placed into the Private Peripheral Bus. Let's zoom in to the Private Peripheral Bus region. This is the lowest one-megabyte chunk of the system memory region. Accesses to this region are always treated as little-endian. As we'll discuss later, the other memory regions can be configured to be treated as big-endian. In general, registers in this section support word accesses only, meaning that in order to access these registers, we have to use an LDR or an STR instruction with 32-bit accesses at a time. There are some exceptions, however, as detailed in the Arm Architecture reference manual for registers that also support byte or half-word aligned accesses. Since this is the Armv8-M, there's also the optional security extension. If the security extension is implemented, then there are duplicated system controls based sections, four kilobytes each, which one, the System Control Space, controls the secure side of things whereas the NS, Non-secure System Control Space controls the Non-secure side of things. In addition to the SCS regions, there are also sections that contain information about the ROM table, the ETM and a TPIU, which are used for trace, that's the Embedded Trace Macrocell and the Trace Port Interface Unit, as well as the Flash Patch Breakpoint unit, the Data Watchpoint and Tracepoint unit, and the ITM, Instrumentation Trace Macrocell. Each of these sections is four-kilobyte in size.
