In this lecture you will learn how to design a voltage control loop around a peak current mode controlled converter. We will rely on the simple model we have derived, and we will use that simple model to construct the output voltage controller that is based on sensing the output voltage, comparing to a reference. and then the key point of the design will be to construct the compensator that in turn will set the control input for the current mode controlled converter. We will do that on a particular example. We'll take the familiar point-of-load buck converter and design the voltage loop around it. So this is going to be a two loop system. And inner current control loop that sets the duty cycle by sensing the inductor current, comparing to a control input, and determining the end of the pulse at a time when the two inputs of the analog comparator in the controller are equal. And then there is an outer voltage loop that we will design in the lecture today. The simulation example will be based on what we have seen earlier. So here is the current mode controlled synchronized buck converter with the current mode controller set to operate at 1 megahertz and with the inputs being the control input Vc and the sense value of the inductor current. What is missing here is the voltage loop compensator and that's what we will design and construct in the lecture, now. The particular numerical values for the design example are shown here. It is a synchronous buck voltage regulator, operating at 1 megahertz switching frequency, and it is expected to deliver a well regulated 1.8 volts across the load from an input voltage that is nominally set to be equal to 5 volts. The inductor is 1 microhenry, the output filter capacitor is 200 microfarads. But that output filter capacitor includes an ESR equivalent series resistance of 0.8 milliohms in the output. For the sensing of the output voltage, the gain is equal to one. We directly sense the output voltage as is and compare it to reference value equal to 1.8 volts. And for the sensing of the current, we assume that the equivalent resistance, that is a scale factor between the inductor current and the voltage Vs that represents that inductor current, is equal to 0.1 ohms. So the control to output transfer function is a starting point for the design of the voltage loop compensator. The output port of the small signal model is very simple, as we have discussed already. The output port includes a control current source that is equal to the control current ic. In turn, the control current is equal to the control voltage divided by the current sense resistance value Rf. The control current or the inductor current, which is approximately equal to the control current by the control action of the peak current mode controlled and the simple approximation, is driving the output which consists of a parallel combination of the output filter capacitor including an equivalent series resistance, and the load resistance. So derivation of the transfer function is really simple. The transfer function from control input to the output, or v hat over vc hat, is simply equal to the output impedance Z, the impedance of the output network Z, divided by Rf. And the expression is 1 over Rf times Rload in parallel with the series combination of Resr and 1 over sC, the impedance of the output filter capacitor. Let's start with the uncompensated loop gain, which is really equal to the Gvc we have just derived. We will employ the algebra on the graph method to construct this uncompensated loop gain and then decide what is a suitable way to construct the voltage loop compensator around that uncompensated loop gain. Let's construct the magnitude response of the uncompensated loop gain using the algebra on the graph method. So we have three components. First, the impedance of the output filter capacitor is 1 over omega C. Second, we have the impedance of the equivalent series resistance that's going to be a flat impedence that is going to dominate the response at high frequencies. And then, we have Rload which can be represented as a flat impedence that dominates at low frequencies. So, this is the value of Rload right here, here's the value of Resr. Now, you see we have a series combination of the capacitor and Resr, so the larger of the two value, quote mark "wins", and so the overall transfer function is going to follow this curve right here. At low frequencies, we have a parallel combinations of Rload, and one over omega C. And in that parallel combination, the smaller value "wins" and we have a complete transfer function shown right here. To be precise we have a scale factor of 1 over Rf in front of everyone of these components. And so we have Rf here over Rf here and over Rf here. Here is the summary of the magnitude response of the uncompensated loop gain that we have just obtained using the algebra on the graph method. For the particular values given in the example we notice that the esr frequency is at round 1 megahertz. It is determined by the time constant of the output filter capacitor, whereas the low frequency pole is determined by the value of the load resistance. Now of course we don't know upfront what the load resistance is going to be. But even for the smallest value of the load resistance that for example, corresponds to a resistive load at five amps of output current. We can safely conclude that that pole is going to be located well below the frequency of 100 kHz. That we will, as you will see in a moment, be used as the desired value for the crossover frequency for the voltage control loop. Given that the uncompensated loop gain of the current mode controlled converter is relatively simple, dominated by the singled pole response associated with the output filter capacitor, we can see that simple PI compensators can be used to close the voltage loop around the converter. A PI compensators has a form as follows. Has a gain of Gm, that we see here as a mid-frequency gain. has an inverted zero of the form (1 + omega_z/s). And that fz frequency, shown right here at low frequencies, you see the integral action that is going to guarantee zero steady state error in closed loop operation of our voltage regulator. And in practice, we can further add a high-frequency pole this over (1 + s over omega_p), notice the minus 1 here. That pole is going to roll off at very high frequencies at a slope of minus 20 dB per decade. So to design the PI compensator, first of all we set the desired crossover frequency to be one-tenth of the switching frequency. So let's say the desired crossover frequency is 100 kHz. Of course you can try desired higher crossover frequency or lower crossover frequency but as an example we will take that crossover frequency to be equal to one-tenth of the switching frequency or 100 kHz. The first point to do here is to select the gain Gm, so that the magnitude response of the compensated loop gain is equal to 1 or 0 dB at frequency equal to fc. fc is going to fall into the region that is dominated by the response of 1 over omega c, the output filter capacitor. And so it is very simple to set up an equation that determines the value of Gm. We have Gm over omega_c C Rf = 1. That will set the crossover frequency at the desired value of 100 kHz using the Gm that is equal to the product of omega_c, C and Rf, that comes out to be equal to 12.6 or 50 dB of midfrequency gain. Then we select the fz, zero frequency in the PI compensator, to be below the crossover frequency so that they end up having adequate phase margin in the system. The phase margin is going to be determined by 180 degrees minus 90 degrees contributed by the response associated with the output filter capacitor minus 90 degrees associated with the integral action of the compensator at low frequencies. So, we have lost a total of 180 degrees because, of these two factors. And the zero in the PI compensator is what brings that phase margin back and that increasing phase margin is going to be dependent on how far the crossover frequency is from the zero frequency. So as an example, if we use fz equal to fc over two, we will end up with a phase margin of about 50 degrees, which we will take as being appropriate in this design example. Finally, for practical purposes, we also select the value of the pole, the high frequency pole that is rolling off the high frequency gain of the circuit in a practical design, and for convenience, we choose that pole frequency to be equal to the ESR zero frequency in the response of the converter, or equal to 1 megahertz. So here is the shape of the of the magnitude response of the compensated loop gain. Notice the integral action at low frequencies, then we have a load after, load frequency that is far below the crossover frequency and makes no impact on the location of crossover frequency. We have minus 40 dB per decade until we hit the zero in the pi compensator. And then we cross the crossover frequency across the zero dB axis, at a crossover frequency with a phase margin determined by how far the zero frequency is from that crossover, and we have designed that to be around 50 degrees. The final step is to implement the PI compensator around an opamp. So, the implementation is very simple. we have direct sensing of the output voltage, we feed the output voltage to the input, negative input of the open through resistor R1. In the feedback circuit around the open, we set up R2 and C2 to determine the zero of the PI compensator. And in parallel, we have an auxiliary small capacitor C3 that is going to set the pole frequency, the high frequency pole in the PI Compensator. The approximate expressions for the gain, and the two frequencies are shown right here. And those can be easily used to find out the particular values of components in the actual circuit implementation of the PI compensator. So let's put this all together. Here is the complete synchronous buck point of load regulator that is current mode controlled. But now notice that the control input to the CPM modulator is the output of the PI compensator we have just designed. So let's see simulation waveforms for a step load transient. Now in the transient simulation of this circuit, the results are shown right here. The output voltage after a start up transient that is not shown here is now regulated at 1.8 volts. Upon a load step, the output voltage dips slightly by about 10 millivolts and returns back to regulation to within around or less than 10 microsecond. Upon the opposite, step load transient we have a slight increase in the output voltage, but the output voltage returns to regulation very quickly, and you can see a very nicely looking step load transient responses in this current mode controlled synchronous buck regulator. Other waveforms shown include the comparison of the control input and the sensed value of the inductor current. And you can see how that sensed value of the inductor current is just touching the value of the control input to the CPM modulator. The bottom waveform shows switch node voltage waveform that is pulsating of course where the duty cycle is adjusted dynamically by the controller in response to the step loads that are shown or illustrated right here. And finally, the top waveform shows the waveform of the inductor current. That is the standard triangular waveshape before the step load, standard triangular wave shape after the step load and has transients in the step-up of the load transient and step-down of the load transient. A little bit of concern is associated with the transient that we have right here. You can see that also a little bit in the output voltage and also in the inductor current. What is going on here? Looks like we have this M-like shaped inductor current waveform during the transient of the wave when the inductor current is stepping up from around zero amps to around two amps. Where is that coming from? That is something that we will try to answer in the next lecture. But to illustrate the point further, if we use exactly the same circuit, but change the reference to 3.3 volts, based on the simple model, we will expect this circuit will perform just as well as a circuit that has a reference voltage of 1.8 volts. However, the waveforms shown by simulation are far, far from nice. You see oscillatory responses in the inductor current. The output voltage doesn't look nice either and there is all kinds of weird behavior in the control input and the sensed value of the current. The switch node voltage looks chaotic, it looks like we are producing pulses in a manner that does not correspond to what we would expect. And of course, there is a question of why does this happen? Our simple model does not predict any of this type of behavior. That's, again, something that we will address in the next lecture. In summary, the simple model results in single pole control to output transfer functions, which means that a simple PI compensator is in general sufficient in the voltage control loop. We can look at a design example around the CPM controlled synchronous buck point of load regulator. But if you also noticed that that same example leads into strange behavior and oscillations that we are not able to explain yet based on what we have learned so far. So in the next lecture, we will examine the nature of these oscillations and the ways to go around them, how to fix the problem that was uncovered in the example that we considered in this lecture.