In the previous lecture, we have derived an average model for the peak current model controller. In this lecture, we will look at how to use that model in design verification. As an example, we will look again at the CPM controlled synchronous buck converter shown right here. This is the switching circuit model with a CPM modulator taking two inputs, the sensed inductor current and the control voltage, and the values are set so that the output of about 1.8 volts is obtained across the load from the input voltage of 5 volts. First we construct an average circuit model. The average circuit model replaces the switches with an average switch model CCM1. Since we have a synchronous rectifier in this converter, we know that the converter always operates in continuous conduction mode and so CCM1 is a convenient average switch model. Similarly, we use CPM-CCM, the CCM-only version of the average model for the peak current mode controller. Let's look at how the model is set up. The two voltage inputs are set up to represent the voltages impressed across the inductor during d Ts and d prime Ts, respectively. So, E1 is equal to the input voltage minus the output voltage. E2 is equal to the output voltage. Those are the voltages that define the slopes m1 and m2 as needed inside the calculations performed in the CPM-CCM average model for the peak current mode controller. Notice that we neglect small voltage drops across the series elements in deciding what voltages to place across the inputs of the two voltage controlled voltage sources E1 and E2. Both of those have gains of one. The sense current is obtained using a current controlled voltage source Hsense and the scale factor, the equivalent current sense resistance, is 0.1 ohms. The control input is set to 0.5 volts, which gives us the steady-state output of about 1.8 volts across the load. And we will also examine the AC responses, setting a small signal AC perturbation of the control input to normalized value of one. Let's look at the AC results. Notice that we have actually performed the AC simulations for the control to output frequency responses for three different values of the parameters of Va, those values of 0 volts, .18 and .36 volts, corresponding to different values of the slope of the artificial ramp. The value of 0.18 volts will be the case when ma, the slope of the artificial ramp, equals m2, the slope of inductor current during the d prime Ts interval. Based on the simple model, recall that for the same example we found the control to output transfer function to behave like a single pole transfer function with the low frequency dominant pole located at 2 kHz and the low frequency gain of 12 dB. For three different values of the slope of the artificial ramp or the parameter Va, which is the amplitude of the artificial ramp, we obtain three, a set of three magnitude responses and corresponding three phase responses for the control to output response. In the magnitude responses, we can notice that there is a slight difference depending on how large the artificial ramp actually is. We will explain those differences analytically when we look at the analytical model resulting from the improved average model for the peak current mode controller. Even more importantly, at high frequencies you see the phase responses that are substantially different. And if you look at around 100 kHz, which may be our target crossover frequency for closing the voltage loop for this 1 megahertz switching power converter, you see significant differences in the phase lag depending on the value of the artificial ramp. So we already see how the simulation model can provide significant information about how important parameters in the CPM controller affect the frequency responses and in turn affect the closed loop voltage regulator design. Let's look at the voltage regulator design that we actually completed last week when we used the simple model to design a simple PI compensator in the voltage loop. So this is the same example, except now we have closed-loop operation with the output voltage sensed, compared to reference equal to 1.8 volts, and processed by a PI compensator to produce the controlled input for the CPM modulator. This is the switching circuit model exactly the same as the one we used earlier to verify operation of the closed-loop voltage regulator by transient simulations of the switching circuit model. Here as a reminder of the waveforms that we have already observed. So for the value of the amplitude of the artificial amp of .18 volts, which is a practical choice of Ma equal to M2, we get nicely looking step-load transient responses with relatively small dip and relatively quick return to regulation at 1.8 volts. The control voltage minus the ramp, compared here to the sense voltage vs in this waveform right here. The top one is the inductor current, and the bottom one is the switching waveform, showing the familiar pattern of pulses, directly corresponding to switching action of the two switches in the converter. Let's construct the average model for this. The model is exactly the same as the average model we have derived before, except now we added in exactly the same manner as the switching circuit model the voltage loop compensators around the op-amp. The PI compensator that is comparing the output voltage to the reference and producing the control input for the peak current mode controller. In order to determine the loop gain, we have inserted a test source, Vz between the output of the PI compensator and the control input of the peak current mode controller. This is the most convenient location for the insertion of the voltage source that can then give us the loop gain simply as the ratio of negative v(y) over v(x). We will again examine the loop gain response for several different values of the amplitude of the artificial ramp, 0.09, 0.18, 0.33, and then a large value of 0.8. And we will use the measurement line to actually evaluate exactly where the crossover frequency is and how much phase margin we have. This will be performed by AC simulations. Before that, let's take a quick look at a transient simulation of exactly the same step load transient we used in the switching circuit simulation. The output voltage has no ripple, but the shape the dynamic response of the output voltage resembles the dynamic response we have observed in the switching circuit. Similarly, the inductor current has no ripple in the average circuit model, but response is very similar in dynamic shape compared to what we obtained in the switching circuit model. The control input shown right here, that's the control input for the current modulator. And it is interesting of course, to show the switch node waveform. which is really the average value of the switch-node waveform. There are no longer any pulses there, but the average value showing a bump in the duty cycle and then a dip in the duty cycle corresponding to the opposite step-load transient. In the simulation that we perform to find the loop gain responses, we already mentioned we do that for four different values of the amplitude of artificial ramp. If you look at magnitude responses, they're all fairly similar with slight difference is in the magnitude responses at low frequencies and some slight differences at high frequencies. The crossover frequency in all cases is pretty close to around 100 kHz, but the phase margin is very different depending on the amplitude of the artificial ramp. It goes from 51 degrees for small value of artificial ramp to 21 degrees for a very large value of the artificial ramp, equal to four times the slope m2. The practical case that we will recommend in most situations is the choice of ma equal to m2. That results in a crossover frequency close to 100 kHz, and close to 45 degrees of phase margin, close to but slightly smaller than the 50 degrees that we have planned to have in the design based on the simple model earlier in the lectures. So corresponding to these four choices the step responses examined for different values of Va. This is now going back to transient simulation. But looking at just the output voltage for four different values of the compensation ramp. Notice that when the phase margin is relatively large, in the first three cases, the responses look nice, whereas in the case where our artificial ramp is too large, we have a small phase margin which corresponds to a transient response upon step-load that has ringing and overshoot in the opposite direction and that ringing takes a considerable amount of time to settle. So that's not very desirable, so this choice here would show a too large value of the artificial ramp. Now of course you can say, what can we do about this design here to regain some of the phase margin that we have apparently lost, compared to what we expected based on the simple model. And the answer to that question, of course there are many approaches we can take. One possible approach is to take the PI compensator zero, and move it back from the value of the crossover frequency over two, to the crossover frequency over three. Move back the zero in the PI compensator to boost up the phase margin around the crossover frequency. And in practice, that would be done simply by increasing the value of the C2 capacitor, the one that determines the location of the PI zero from 220 pF to 330 pF. So if you repeat the simulations in transient for step-load transient, for the four values of the artificial slope amplitude that we have examined earlier, we see now that in the case of a large amplitude of the artificial ramp we have a more damped response than we had previously, which is because we have regained some of the phase margin lost because of the high frequency effects associated with the large artificial ramp slope. The phase margin for what we will consider here, a nominal case with the choice of artificial m equal to the m2 slope. we're back to more than 50 degrees of phase margin, and we have nicely behaved step load transient responses. Now of course this was just one possible example of how design verification and design modifications can be performed based on the Spice circuit model that we have in average sense for the peak current mode controller. Those models are well suited for DC, Transient, and small-signal AC simulations, and of course, can be done in any number of other particular cases that you may I want to examine. One particular issue that I wanted to bring up in this lecture is the trade-off associated with the artificial ramp. We already know that a sufficiently large artificial ramp is really necessary in a practical design to ensure stability of the controller for all duty cycles, and also to reduce sensitivity to noise. So there is no question that you would want to use an artificial ramp in a peak current mode controlled converter. On the other hand, too large of an artificial ramp results in additional high-frequency dynamics that are not well predicted by the simple model. We're going to look ahead into lectures that follow and find out where these high frequency events are coming from. But right now we know that by simulation those effects can result in reduced phase margin and inadequate responses in a closed loop voltage regulator if the artificial ramp is too large. A good practical choice in most cases is the slope of the artificial ramp equal to the slope of the inductor current in the second subinterval in the d prime Ts interval. Finally, we should note that the developed average model is not able to predict instability of the current mode control for duty cycles greater than .5 when the artificial slope is equal to zero. The model is also not able to predict very well frequency responses at high frequencies when the artificial ramp is small. The assumption is that an adequate amount of artificial ramp is added, in which case the average model that we have developed and implemented as a Spice subcircuit is more than adequate for design verification of peak current mode controlled converters.