In this video, I will demonstrate how to simulate FSM,

that is being driven by a analog to digital converter,

which is typically how these FSMs are implemented,

because the analog to digital converter is actually providing new input

to the FSM to transition between the different mode of operation.

So we are going to follow the explanation that we saw in a previous video,

where we have a finite-state machine, a deterministic one,

and every time that an ADC will essentially have an event of sampling,

it will evaluate whether that transition of mole should happen or not.

Essentially, what we have is now is a serious interconnection of an ADC,

where the input of ADC will be created by some single,

and the output of ADC will drive the finite-state machine.

So we already prepared that here for us,

and this is the model.

This is essentially, the finite-state machine that we want to implement.

We're going to use the same machine that we described in a previous video,

where we have three modes of operation,

A, B and C,

and we will code them then as one, two,

and three, and the inputs were either zero or one.

So with this initialization file,

what we are going to sort is

the initial state of the finite-state machine to be Q equal one or Q equal eight,

and then zero for the analog to reach the [inaudible] states with a memory and the timer,

and the same sampling rate which is given by almost

0.4 the value that we use in a previous videos as well.

We are going to run this for three seconds and no more than 20 jumps and

using the usual rule and tolerances choices.

So, we're going to run the initialization files,

so we get things going.

And that sounds what we expect to see the rate for samplings about zero point,

a little bit below 0.4 seconds.

So, the finite-state machine itself has the input that we

actually have applied to the finite-state machine in a previous video,

where we only were illustrating how to simulate

a finite-state machine using the Hybrid Equation Toolbox.

Now we sample that same now using the rate that we find from a sample four seconds.

So we're ready to run the simulation.

Completion takes place.

This simulation runs and it looks like it got too close to three seconds.

Now let's plot the result using the postprocessing function.

And what we see here is that,

the input that is being created that originally

was sent to the finite-state machine but now has been

sampled by the analog to digital converter,

changes from zero to one at around 0.4 so seconds.

But that information is only appearing in

the output of the analog

to digital converter which drives the FSM almost around 0.4 seconds later,

which is the rate that we have here.

At that very time is when the input

goes from zero to one and generates a transition from Q point one to Q point 2,

since the input remains at one after that transition.

There is another transition that makes

the state of the finite-state machine go from two to three,

and then as we described [inaudible] machine in the past,

in a previous video, the state Q equal three is an environment for

the machine not remain stuck forever.

And it doesn't matter what kind of inputs being applied in the future.

So that's a simulation of an interconnection, in this case,

a serious interconnection of analog to

digital converter driving a finite-state machine which actually implements

the finite-state machine with a device that provides inputs at periodic times instance.