[MUSIC] In this first lesson of the last week we are going to briefly present two types of Physical Implementation of digital circuits. All along the course, we have learned to generate digital circuits made up of gates, flip flops, and other components, so the result of our development work is a logic diagram of this type. Now, the question is: how can we physically implement our circuit? How can we build a real circuit like this one? The first option is to use small scale or medium scale integrated circuits and to interconnect them on a printed circuit board like in this example. But another option is to design and manufacture a new integrated circuit. Here are two examples of very simple standard chips: a chip that integrates four two input AND gates and here another chip that integrated three 3-input NOR gates. The corresponding logic diagrams are this one and this one. The vendor gives the user data sheets that define, for example, the electrical characteristics of the circuits, the logic functions they implement, and also the relation between the internal components, the four AND gates in this case, and the package pins. For example, the second input of this AND gate corresponds to pin number 8. Then all the chips, all those standard chips can be connected to a prototyping board like this one, and connections between the chips are implemented with small wires like those ones. And finally, a printed circuit board is fabricated. It includes the holes within which the chip pins will be inserted and the connection tracks like this one between the pins. Now, this is a convenient option for small circuits, but in the case of large circuits a better option is the development of a new integrated circuit, a so-called application-specific integrated circuit (an ASIC) that integrates the whole circuit. This is an example of integrated circuit. Then within the package, there is a small silicon die here that integrates the whole circuit. You can see that the die is connected by very thin wires (here, for example), very thin wires to small tracks like this one, within the package. And those tracks in turn are connected to the external pins of the package. The technology used to manufacture integrated circuits is MICROELECTRONICS. It allows integrating electronic circuits on a semiconductor substrate, most often SILICON. The fabrication consists of several processes, such as oxidation of the silicon wafer, deposition of some layer, etching of the deposited layer, iron implementations and others. And most of those processes use a mask. Actually, at each step certain areas must be masked out. As an example, p-type transistors are integrated within so-called n-type wells, wells that are created by implanting negative ions within the corresponding area. So, some masking technique must be used in order to implant negative ions only within the p-type transistor areas. Integration density of those integrated circuits is very high. As an example, the Intel core i7 includes more than 700 millions transistors. The information that an IC (an integrated circuit) production line, a so-called silicon foundry, needs to manufacture an IC is the so-called LAYOUT: it is the geometric information that allows fabricating the masks. To most fabrication steps corresponds a specific mask. For example, a specific mask to define the active areas, that is to say, the areas where there are transistors; the p-diffusion areas corresponding to the areas where there are p-type transistors, and so on. This is a silicon wafer and each square is an integrated circuit. So, a lot of circuits are manufactured at the same time. After the complete processing of the wafer, the wafer must be cutted. It's the so-called dicing process and each die must be encapsulated within a package. The generation of the layout, from a logic diagram, is not an easy task. As an example, this is the layout that corresponds to a CMOS inverter (to this circuit). It is a circuit that consists of only two transistors, one n-type and one p-type transistor. For example, the blue areas like this one correspond to metal tracks. The red areas correspond to transistor gates (this is the gate of the n-type transistor and this is the gate of the p-type transistor) that are connected and are the input of the inverter. The green areas, like this one and this one, are n-type or p-type areas, the sources and drains of the transistors. The yellow area is the n-type well that I've mentioned before, and so on. The conclusion is that, to design a circuit, integrating hundreds of thousands of logic gates, it is necessary to generate millions of eometric forms, with several layer types (each color in this layout corresponds to a different layer). taking into account design rules such as the minimum width of a transistor or the minimum distance between two different metal tracks, and so on; and furthermore, it's necessary to compute the size of the geometric forms. As an example, the delay of a gate depends on the size of the corresponding transistors. Then, how can we manage such a complex task? The answer is: we must use implementation strategies, and some of them are: Standard Cell approach, Gate Array approach, Field Programmable Gate Aarrays, and it necessary to develop and to use automated synthesis tools. And this will be the subject of the next lesson. Thus, summary of this lesson: digital circuits can be implemented with Small-Scale and Medium-Scale integrated circuits interconnected on a printed circuit board. But another option is the development of an Application Specific Integrated Circuit (an ASIC) that allows integrating up to millions of transistors. The layout definition is a very complex task, and to manage that complexity we need implementation strategies and we need software tools. [BLANK_AUDIO]
