[MUSIC] The five blocks that constitute the structure of our processor, have been implemented and VHDL models have been generated. To complete our design, it remains to assemble the five blocks. Previously, we must choose an encoding of the instructions. Up to now we have always used names such as ASSIGN VALUE, DATA INPUT, and so on, to identify he instructions as well as a list of parameters such as index K, value A, and so on. Obviously, to implement a circuit, those names (sometimes called mnemonics) must be encoded under the form of binary vectors. This table describes a possible way to encode the instructions: 4 bits, C15 down to C12, encode the instruction name as well as the operation to be performed in the case of the OPERATION instruction (addition or subtraction), and 12 bits are necessary to define the instruction parameters. For example, in the case of an operation instruction, there are three indexes, I, J and K, and each of them is a 4-bit vector. Another example in an ASSIGN VALUE instruction: there are two parameters: a number A, an m-bit vector, and an index K, a 4-bit vector. Furthermore, the instruction encoding has been chosen in such a way that the generation of the control signals will be easy. Remember that we have computed (in a previous lesson) that the minimum number of bits to completely encode all possible instructions is equal to 15. So, this encoding that we propose, and will make the control signal generation very easy, with only one bit more (16) than a minimized random encoding (15) seems to be a good one. Let us now generate the control signals, taking into account the definition and the instruction name encoding. From the table that defines the control signal of the INPUT SELECTION block, this table, and from the instruction code. we can see that the input control bits correspond to bits number 14 and 13 of the code of the corresponding instruction name. As regards the parameters, G is defined by bits number 7 down to 4 (actually, 6 down to 4 because there are only 8 input ports so that bit number 7 is not used) and constant A is equal to bits number 11 down to 4. So, in this case, all control signals and all parameters are included within the instruction and are directly extracted from the instruction. Next block is the computation resource. In this case the only control signal is bit f; when equal to 0 the operation is an addition, and when equal to 1 the operation is a subtraction. So, f is simply bit number 12 of the encoded instruction. Next block is the OUTPUT SELECTION block. The control signals are output enable and output selection; as regards output enable, it must be equal to 1 in the case of an output operation. So, this control signal must be equal to 1 when bits number 15 and 14 of the instruction code are 1 0, and the Boolean expression is out_en = C15ÀNOT(C14). The output selection makes the difference between DATA OUTPUT and OUTPUT VALUE; so, you can use bit number 13 for that. As regards the parameters, you can see that I is equal to bits 10 down to 8 (10 and not 11 because there are only 8 output posts), and the value A is given by instruction bits number 7 down to 0. Now, the register bank: the write_reg control signal of the register bank is equal to 1 when bit number 15 is equal to 0. So that write_reg is equal to NOT(C15), and the indexes I, J and K are equal to C11 down to 8 in the case of I, J is equal to C7 down to 4, and K to C3 down to 0. Finally, the numb_sel signals of the go_to block, you can observe that they're directly defined by bits number 15 down to 12, and the parameter N is given by bits 7 down to 0. And this is the complete circuit, with it's five blocks: INPUT SELECTION, REGISTER BANK, COMPUTATION RESOURCES, OUTPUT SELECTION, and GO TO block. Practically all control signals and parameters are directly extracted from the instruction, that is bits 15 down to 0. It only remains to generate write_reg = NOT(C15) and out_en = C15ÀNOT(C14). Let us now generate a VHDL model. This is the entity declaration. The inputs are the eight input ports of the processor; the instruction, an n-bit vector; 2 bits "clk" and "reset" (here is "reset" and the clock is not represented); in this circuit there are eight outputs The eight output ports of the processor and a bidirectional port "number", an 8 bit vector that gives the number of the next instruction to be executed. Within the architecture several signals must be declared: two control signals write_reg and out_en, and those m-bit signals "result", "reg_in", "left_out" and "right_out". Then all components, that is to say the five blocks, are declared. For example, this is the INPUT SELECTION component declaration. It's practically the same as the entity declaration. And the same for components COMPUTATION RESOURCES, OUTPUT SELECTION, REGISTER BANK and GO_TO block. It remains to instantiate the five components. For example, component INPUT SELECTION is instantiated: to the logical names IN0, IN1, and so on, are associated the actual signals IN0, IN1, and so on. In this case the names are the same. To the logical name "A" are associated bits 11 down to 4 of the instruction. To the logical name "result" the signal name "result", to the logical name J the instruction bits 6 down to 4, to the logical name "input_control" bits 14 down to 13 of the instruction and, finally, to the name "to_reg" the signal reg_in. And the same for all other components: COMPUTATION RESOURCES, OUTPUT SELECTION, REGISTER BANK and GO_TO block. Finally there are two Boolean equations corresponding to write_reg and out_en: out_en is the AND function of bit 15 of the instruction and bit 14 o the instruction inverted, and write_reg is equal to bit 15 of the instruction inverted. And that's all. Summary of this lesson. The set of instructions have been encoded with 16 bits. The control signals has been generated from those encoded instructions. The complete processor has been implemented and a VHDL model has been generated.