[MUSIC] I see you have arrived, our new secret agent recruit. As you know, we work for Q. We deal with Quartus, Q-Sys, quick logic, and other quandaries. >> Are we part of the Q Continuum? >> Different Q. >> Okay. >> This is my friend Ben. Also a secret agent. >> Not a secret anymore. >> I'm Tim Scherr, and this is our special guest lecturer for course two of the specialization, Ben Spriggs. >> Hi, and welcome to Hardware Description Languages for Logic Design. We will be your guide for the next several weeks as we reveal the secrets of HDLs. >> Already talking in code. So what are we going to tell them about these secrets? >> Yes, it's our mission to guide these people to learn new languages. >> Do you have to travel to a foreign country to learn new languages? >> No, they can learn them from home, at work, or anywhere, via the power of the Coursera platform and our help. >> I'm ready to tell them the first secret. What are we going to uncover? >> They will learn secret hardware description languages. >> All right. They will learn how to design logic by writing code in VHDL. >> Yeah. >> We will also teach them how to design logic by writing code in Verilog. >> What? Why would anyone want to learn Verilog if they already know VHDL? >> Because it's the clearly superior language for digital design. >> But Verilog is case sensitive. Why would anyone want to deal with that? >> Well, VHDL is strongly typed. Why would anyone want to hassle with that? >> You've got to be kidding me? What kind of a mission is this? I'm not supporting anything Verilog. >> I'll tell you what. Let's present both VHDL and Verilog with lots of good examples and let people come to their own conclusion. May the best HDL win. >> All right, we know which one that one will be. >> Seriously, Ben and I will have you covered. I have 30 plus years experience designing programmable logic. I produce working circuits for mass production using all the major FPGA vendors, Intel Altera, Xilinx, Microsemi, and Lattice. And Ben has almost as many years doing ASIC design for several major networking and storage companies. >> Yes, and even ASIC simulation using FPGAs. >> So it's time to cue the next video. >> You know what they call Engineers trying to do comedy? >> No. >> A license to kill, time, that is. >> Okay, I can't promise there won't be some bad puns, but there should be some good things to learn. I can promise, though, there will be no dancing. >> Engineers dancing, nobody wants that. [MUSIC] I think you missed your cue. >> Time to begin. Cue the music. >> And if you think this is exciting, wait until you learn all about VHDL. >> And Verilog. Your mission awaits. >> VHDL first. >> Prepare for your first mission. This video will terminate in five seconds. [MUSIC]