Introduction to Hardware Description Languages for FPGA Design - Basics of VHDL | Coursera

Introduction to Hardware Description Languages for FPGA Design

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University of Colorado Boulder

Hardware Description Languages for FPGA Design

University of Colorado Boulder

4.4 (504 ratings)

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28K Students Enrolled

Course 2 of 4 in the FPGA Design for Embedded Systems Specialization

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This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.

Skills You'll Learn

Writing Code in Verilog, Simulating FPGA Designs, Designing FPGA Logic, Designing Test Benches, Writing code in VHDL

Reviews

4.4 (504 ratings)

5 stars
58.92%
4 stars
27.97%
3 stars
6.94%
2 stars
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1 star
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KK

Jun 4, 2020

This is very good course , but i found some little missing details related to reading materials .

But this was really very helpful course for me as fresher .

KP

Oct 27, 2020

I think this is a good start in learning how to write VHDL and Verilog.

I would like to see a next level course or recommendations for further writing code.

From the lesson

Basics of VHDL

This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.

Introduction to Hardware Description Languages for FPGA Design4:05

Taught By

Timothy Scherr
Senior Instructor and Professor of Engineering Practice
Benjamin Spriggs
Lecturer and Scholar of Engineering Practice

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