What I am going to show you in this class is an example on how to implement a simple behaviour on a simplified FPGA device. First of all we do have to recall some definitions we should be already familiar with anyhow. As we know, an FPGA is an heterogenous device made of different elements. Among those elements we can list: Configurable Logic Blocks, or CLBs, used to implement combinational and sequential logic. I/O blocks that are special logic blocks at the periphery of the device used for external connections and last but not least...interconnections Those are wires, and not only, used to connect Inputs/Outputs to configurable logic blocks. The FPGA we are going to work with is a supersimplified version of a real complex Field Programmable Gate Array. As it is shown in the figure our device is a two times 2 CLBs FPGA. We are going to number our CLBs starting from the top left corner in a top-down, left-to-right column-wise way. The same thing is happening with respect to our I/O blocks. As we can see, we do have 8 I/O blocks but, because of the way in which the device has been embedded in a larger system, a board, just to give you an example, six of them are used as inputs while the remaining two are output blocks. Now, what I have here in my hand is a PYNQ-Z1 board. The FPGA available on this board is the Xilinx Zynq-7000 SoC but where is it? We can see several elements, but which one of them is our FPGA? Well, the FPGA is this black square just right here, right in the middle of the PYNQ board. Now, going back to our example: when I was saying “because of the way in which the device has been embedded in a larger system”, well, that is exactly what I’m talking about. The device has a set of I/O blocks, but it depends on how it has been integrated into a board to know exactly the nature of each of them. With respect to the structure of our CLBs, since we are working with a simplified FPGA, we can also simply the structure of the CLB. We know that they are defined in a hierarchical way by a set of Slices and that each Slice contains a certain number of LUT, but here, just for sake of simplicity, we are going to collapse everything and we are going to assume a one CLB - one LUT model. The CLB can be used to implement both combinational and sequential logic. The LUT is used to implement a certain logic function which means that, if we want to implement a sequential logic, we do need to add a FLIP-FLOP to the CLB and a multiplexer to select in-between the combinational and the sequential solution. In our example also the LUT has been simplified. Usually, it is a 4-inputs, 1 output, but here it has been designed to implement a 2-input - 1-output logic. Given this set of element, to configure our CLB we need 5 bits. Four are going to be used to set the value in the LUT to implement the desired functionality, while the fifth one, will be used to properly set the input, named here L, of the multiplexer. Once that the CLBs and the I/O blocks have been described, we are missing just one more element of our FPGA... the interconnections. Interconnections will be implemented by using a set of PROGRAMMABLE SWITCH BOXES. Because of the given setting, each Switch Box is routing the signal of three lines. At the end, as the name is suggesting, a PROGRAMMABLE SWITCH BOX is a box of PROGRAMMABLE SWITCHES. In this figure we are appreciating the boundaries for the switch box represented by the dotted line, while the the switch matrices, the interconnection points, have been represented by the green square at the cross of two lines. The way in which a switch box is routing a signal is done by properly configuring the interconnection point, but to do this we have to see how these elements are implemented. As we may recall a PROGRAMMABLE SWITCH MATRIX is realised by grouping together a set of six PROGRAMMABLE SWITCHES. Each PROGRAMMABLE SWITCH is implemented by using a PASS-TRANSISTOR. In the figure we can see how the six pass-transistors are connected to implement the switch matrix Within this context, configuring a programmable switch matrix means that we do have to provide the configuration of the six programmable switches. This is done by numbering each programmable switches to define a sequence of six bit as the configuration of the programmable switch matrix. Furthermore, considering that the Switch Box is made of three programmable switch matrixes, this means that we need 18 bits into our configuration memory to store the configuration for each one of our switch boxes.