We are almost there. We have the final design ready to be implemented but, as we know, this is not enough, we are not done yet. We need to “translate” our solution, our design, into “something” that can be used to properly configure the FPGA. We are not new to it... come on, I know, that you know it... That’s right! We need to create our CONFIGURATION BITSTREAM! To be able to create our configuration bitstream we have to go through the final step of our design... the BITSTREAM GENERATION PHASE. This phase will translate our design into a sequence of zeros and ones, stored into the CONFIGURATION MEMORY. Within this context, what we are looking for is basically the set of rules used to create the correct sequence/translation. We are going to start with the functionality that has to be used to configure CLBx. As we know, because of the previous phases, CLBx has to be configured with an OR gate and a flip-flop. Because of the chosen FPGA, we also have all the information about its internal structure. We know that they have a 4-bit LUT that can be used to implement a 2-inputs, 1-output logic, therefore what is need is the way to store in the configuration memory for the LUT the OR function. Furthermore, we now that we are not going to implement a combinational logic but a sequential one which means that we have also to configure the multiplexer connected to the output to capture this scenario. To do this we need to know how the configuration memory is organised. Usually this is a hidden information, FPGAs vendors are not willing to share this information to protect the IP designers. Why? Well, it is quite simple. If I know how the configuration memory is built/organized and I have a configuration bitstream of an IP that I’m interested in using, this means that I can reverse engineer the design of the IP by knowing how it will be implemented onto the FPGA elements. In our context things are quite different, we are here to try to understand how things are working, therefore we can make simplifications of the real context and we can provide/share this information for teaching purposes. So, let’s go back to our bitstream generation phase. We know that our LUT can configure a 2-input logic, and we do have to choose in between combinational and sequential, this means that, at least, our configuration memories need to have 5-bit to store the configuration of a generic CLB with these characteristics. Now, we have to configure an OR logic, which has a known TRUTH-TABLE, zero, one, one, one, but what is missing is the “location” of these four bits into the sequence of five available in the configuration memory. In this example we are considering the first 4 bits in the configuration memory to be used to host the configuration of the logic to be implemented in the LUT. Now, we are just missing the last bit of information. We know that we have to set the multiplexer to implement a combinational or sequential logic. We know that we just have one more bit available in the configuration memory sequence, the 5th, therefore the location of the information is not an issue, but we do not know yet which value of the bit corresponds to which logic. In our example we are going to assume one to implement the sequential logic and zero for the combinational one. At this point we have all we need to create the correct sequence to be stored in the configuration memory corresponding to CLBx. This configuration is: zero, one, one, one, for the OR logic implemented by the LUT and a final one for the flip-flop. Now, moving to the configuration memory of CLBy, we have to go through the same process we did to configure CLBx, but we can now skip all the details related to the mapping in between the configuration memory and the FPGA elements. We can do this because these are going to be the same, considering that we are working with the same FPGA. So, let’s just focus on the functionality that has to be implemented. This functionality is an AND logic and, as in the case of the OR, its TRUTH TABLE is well known and it is: zero, zero, zero, one. We know that we are now considering the case of a combinational logic, which means that we are going to store a zero in the fifth element of our configuration memory. With all this information we can now say that the bitstream to properly configure the configuration memory behind CLBy is: zero, zero, zero, one, zero