From the mid-1980s, reconfigurable computing has become a popular field due to the FIELD PROGRAMMABLE GATE ARRAY, or FPGA, technology progress. FPGAs, are a particular family of integrated circuits intended for CUSTOM HARDWARE IMPLEMENTATION, with the key property of being capable of RECONFIGURATION FOR AN INFINITE NUMBER OF TIMES. Currently FPGAS are the state of the art of Programmable Logic Devices, and this is the reason why this course is focusing on these particular chips. Reconfiguring an FPGA means changing its functionality to support a new application, and it is equal to have some new piece of hardware, mapped on the FPGA chip, having to implement a new functionality. In other words FPGAs make it possible to have custom-designed high-density hardware in an electronic circuit, with the added bonus of having the possibility of changing it whenever there is the need, even while the whole application is still running. All that glitters is not gold and the VERSATILITY and REPROGRAMMABILITY of Field Programmable Gate Arrays comes at a price. Only a few years ago, the algorithms that could be implemented in a single FPGA chip were fairly small. At the beginning of the century, as an example, the largest FPGA could be programmed for circuits of about 15 thousands logic gates at most. Now, to give you an idea of how much 15 thousands logic gates are, think that a fast 32-bit adder requires a couple of hundred gates, therefore you can easily see that the capabilities of such devices were somewhat restricted. More recently, though, FPGAs have reached a size where it is possible to implement more than reasonable portions of an application in a single FPGA... well, not only portion but, in some cases, the entire application itself. Not only, nowadays we can find FPGAs in th cloud, like in the Amazon F1 instances. Moreover, the “incorporation” of reconfigurable array logic into a microprocessor provides an alternative growth path that allows APPLICATION SPECIALISATION while benefiting from the full effects of commoditisation. Like modern reconfigurable logic arrays, a single microprocessor design can be employed in a wide variety of applications. APPLICATION ACCELERATION and SYSTEM ADAPTATION can be achieved by specialising the reconfigurable logic in the target system or application. This has led to a new concept for computing: if a processor can be coupled with one or more FPGA-like devices, it could in theory support a specialised application specific circuit for each program, or even for each stage of a program's execution. The unlimited reconfigurability of an FPGA permits a continuous sequence of custom circuits to be employed, each optimised for the task of the moment. In the simplest scenario, which can be termed COMPILE TIME RECONFIGURATION (CTR), the configuration of the FPGA is loaded at the end of the design phase, and it remains the same throughout the whole time the application is running. In order to change the configuration one has to stop the computation, reconfigure the chip, resetting it, and then start the new application. Compile Time Reconfiguration was for some years the only kind of reconfiguration available for FPGAs. With the evolution of technology, though, it became possible to considerably reduce the time needed for the chip reconfiguration: this made it possible to reconfigure the FPGA between different stages of its computation since the induced time overhead could be considered acceptable. This process is called RUN TIME RECONFIGURATION (RTR), and the FPGA is said to be DYNAMICALLY RECONFIGURABLE. Run Time Reconfiguration can be exploited by creating what can be considered as a VIRTUAL HARDWARE, in analogy with the concept of virtual memory in general computers. Consider, for instance, an application that is too big to fit into a particular FPGA: the designer can partition it into smaller tasks, each one fitting on the chip. Then it is possible to load task 1 on the chip, execute it, then reconfigure the FPGA for task 2 and execute it, and so on until task n is finished. This idea is called time partitioning, and has been studied extensively in the literature. A further improvement in FPGA technology allows modern boards to reconfigure only SOME of the logic gates, leaving the other ones unchanged. This PARTIAL RECONFIGURATION is of course much faster in case only a small part of the FPGA logic needs to be changed. When both these features are available, the FPGA is referred to be PARTIALLY DYNAMICALLY RECONFIGURABLE. Although there are several techniques to exploit partial reconfiguration, there are only a few approaches for frameworks and tools to design dynamic reconfigurable PROGRAMMABLE SYSTEM-ON-CHIP or PSoC.