CONFIGURABLE LOGIC BLOCKS, from now on called CLBs, are the main components of an FPGA. These elements are the ones that are going to be configured to implement our logic. These elements can be used to implement either combinational or sequential logic. A CLB can be seen as a prefab construction that can be customised according to the user needs. The same starting building block can be updated to meet new requirements, as an example, a block can be used as a single apartment or it can be used just as a studio or even a garage or just as a storage. We can use, or if you prefer, configure them as needed but at the cost of loosing a bit in “performance”, that, in the context of a prefab construction can be seen as comfort room. But let’s take into consideration the case in which more room will be needed. We can overcame the limitation imposed by the usage of a single block by COMBINING TOGETHER more of them, which is the same thing that can be done with CLBs. In Xilinx FPGAs a single CLB is a hierarchical structure composed of a set of SLICES, that are, at the same time, composed of a set of LOOK-UP TABLES. The number of slices can vary according to the device, but in general a CLB contains a set of two slices, which is the case for the Virtex-E, V5 or the 7 Series, while four slices were present in the Virtex II Pro and Virtex 4 devices. A slice, in turn, contains two LOOK-UP TABLES and the necessary interconnect hardware. The look-up tables are elements that can be used to implement, in general, 4-input, 1 output functions. Newest FPGA, like the Xilinx 7 Series, are composed by look-up tables that can be used to implement functions characterised by 6-inputs and 2 outputs. In the figure we can see a 2-slice Virtex-E CLB. This CLB is composed by two slices, each of them containing 2 lookup table. Therefore, at the end, the CLB is composed by 4 look-up table. Look-up tables (LUT) can implement an arbitrary logic function according to their configuration. At the end of the day, a look-up table, in an FPGA, is nothing more than a memory containing Memory Cells to implement small logic function. Let us now see how a 4-bit LUT can be used to implement a 4-inputs, 1-output function. A 4-bit LUT is composed by 16 memory cells, in fact 4 inputs bit can be used to address 2 to the power of four elements. Within this context, we can now use these 16 cells to store the 1-bit output, corresponding to each specific input, of the desired function, no matter its complexity. Given a generic logic function f of 4 binary inputs, A, B, C and D, a “configuration” of the inputs is therefore equal to a number going from 0 to 15. This is done because, as we know, four binary inputs can generate 2 to the power of 4 possibile input combinations of unique numbers. The memory cells need to be just 1-bit wide and the bit stored into them is going to be nothing more than the output of the Truth Table that is used to define the logic function that has to be implemented. Do not worry, we are going to see more on this with some examples. Within this context, configuring a LUT means to properly store the necessary sequence of zeros and ones in the 16 memory cells, according to the desired function. Each line is then connect to a multiplexer which is used to read the output of the function we are looking for by selecting/connecting the desired memory cell, via the proper configuration of the multiplexer, set by reading the A, B, C, D inputs, to the output signal of the look-up table. Around the LUT there is the INTERCONNECT LOGIC that ROUTES SIGNALS to and from the LUT, implemented using standard logic gates, multiplexers, and latches. Therefore, during the configuration process of an FPGA, the memory inside the look-up tables is written to IMPLEMENT A REQUIRED FUNCTION, and the logic around it is configured to route the signals correctly in order to build a more complex system around this basic building block. The INPUT OUTPUT BLOCKS (IOBs) have the function of interconnecting the signals of the internal logic to an output pin of the FPGA package. There is one and only one IOB for every I/O pin of the chip package. The IOBs have their own configuration memory, storing the voltage standards to which the pin must comply and configuring the direction of the communication on it, making it possible to establish mono-directional links in either way or also bidirectional ones. The Input Output Blocks can be seen as a standard Input Output interfaces that we may be already familiar with, as a mic input jack or an audio output one. Now one of the thing which is quite interesting to be noticed is that the I/O pin will be physically bind with external component by the board vendor, therefore, whenever you are going to be interested in using a certain board instead of another one, please be careful in checking the connectivities before implementing your design! Finally, the interconnection resources within an FPGA allow the arbitrary connection of CLBs and IOBs. The main modes of interconnections are DIRECT and SEGMENTED. We are going to see more on the interconnections in the following lecture, because they deserve some time to be properly described.