Welcome to FPGA Design for Embedded Systems. In this video, you will learn how to integrate IP from Intel Altera into a Qsys Design. Perhaps some of the easiest ways to incorporate IP blocks in your design. The remarkable range Altera provides as IP Cores includes soft processors, interfaces to hard processors, DSP, Serial ports, AXI, APB buses, transceiver interfaces, memory, audio, video, and control. To access the IP cores, we first start the Quartus FPGA design tool, create a new project with our target device, and then use the Qsys tool shown here. The left pane contains the IP catalog of IP blocks, which have interfaces which allow them to be connected with in the Qsys system design tool. Let's look at a demonstration of how this is done. Altera has a wide range of IP cores for Qsys available at no cost. I'd like to highlight some in particular. For processors in the embedded category, the AXI Bus Bridge, the vectored interrupt controller, the series 5 hard processor system interface and of course, the Neos 232 bits off processor along with custom instruction translators. For interface, all the Avalon memory mapped in streaming bus interfaces, the APB Master and the Rapid IO II, PCI Express, DMA ingest the 204 B high speed interfaces. For communications, the Viterbi coder decoder, one of many codecs, the RDAU ART, the IEEE 1588 time of day synchronizer, the 10 Gigabit Ethernet Mac and the TSC triple speed Ethernet Mac. For DSP floating point multiplier in EFT. For memory 2 Port Fifo, DDR3 and LP DDR2 DRAM controllers, the SD card and compact flash interfaces. For audio, video and image, the 2D for filter that is 4K ready, the display port interface and the 4K ready Gamma Corrector. For utility, the J tag to Avalon Master Bridge, the remote update, the internal oscillator and NCO. The signal tattoo logic Analyzer Intrasystem, which is essential to high speed debugging. And lastly, for security the SCU or single event upset detection, high speed Reed Solomon Cody decoder, and the random number generator. And Lastly, for security the SCU or single event upset detector, the high speed Reed Solomon coder decoder and the random number generator. In summary, in this video you have learned how to integrate IP from Intel Altera into a Qsys design. Perhaps one of the easiest ways to incorporate IP blocks in your design. You've also learned about the remarkable range Altera provides as IP cores, including processors, DSP buses, transceiver interfaces, memory and control blocks.