Welcome to FPGA design for embedded systems. This video is about logic analysis for SignalTap II. In this video, you will learn how to use the SignalTap internal Logic Analyzer or ILA for EPG hardware debugging. How to analyze signals internal to the FPGA without external probes, they may cause some signal integrity issues. To understand the limitations of internal Logic Analyzers which require FPGA fabric resources. FPGAs and Programmable SoC devices are beginning to receive more and more support, both for our manufacturers themselves and from the tool vendors. The manufacturers have tools that not only include the HDL compilers and fitters, but also programming tools, IDEs for software development and internal Logic Analyzers for hardware debugging. The offering of IP cores has vastly increased in just the past couple of years as well. In this presentation, we will focus on SignalTap II, the internal Logic Analyzer from Altera. Secret agents sometimes have to acquire information by stealth and finesse, breaking into a previously untapped warehouse of information, and then taking pictures and leaving without a trace. We have this capability to take pictures of the internal behavior of an FPGA using the SignalTap II Internal Logic Analyzer. Here's the problem that's been developing over time. As the density of FPGA devices increases, so does the impracticality of attaching test equipment probes to these devices under test. Reflections and other transmission line effects make it very difficult to see the signals. The answer to this is that Altera provides the SignalTap II Logic Analyzer to help with the process of design debugging. This Logic Analyzers are solution that allows you to examine the behavior of internal signals without using extra IO pins while the design is running at full-speed on an FPGA device. Let's introduce the SignalTap II, the SignalTap II Logic Analyzer is scalable, easy to use, and is available as a stand alone package or included with the Quartus software tool. The Logic Analyzer helps debug an EPGA design by probing the state of internal signals in the design without the use of external equipment. Defining custom trigger condition logic provides greater accuracy and approves the ability to isolate problems. The SignalTap II Logic Analyzer does not require external probes or changes to the design files to capture the state of internal nodes or IO pins in the design. All captured signal data is conveniently stored in device memory until you're ready to read and analyze the data. Here is a diagram of the SignalTap II Internal Logic Analyzer. Nodes in the circuit that need to be probed are attached through routing resources in the FPGA fabric to buffers in memory. They're also created in FPGA fabric that collect the data from these nodes. The analyzer communicates the results of data acquisition via JTAG to a PC. This is a equipment setup that you already have likely where you have a JTAG cable that's plugged into your board connected to your PC. You don't need to add anything else in order to use the SignalTap II Logic Analyzer. No external probes or pins are required, just JTAG. This is the design flow for the signal tap Internal Logic Analyzer. The analyzer is started from the tools menu in Quartus needs to be configured with nodes to monitor and triggers for acquisition. The FPGA design needs to be recompiled then to include the analyzer logic in the design before testing. To start SignalTap II, you start Quartus prime first with an existing project, and then you can select tools and SignalTap II, the Logic Analyzer as shown here. The SignalTap II Analyzer will start with a preloaded instance which you can use or you can rename it or you can create other instances if you like. At this point, you will need to attach a development board with that existing design running so that once your device is connected, you want to set the JTAG configuration, and that's done in the upper right part of the screen in SignalTap II, and then here you're going to choose setup, and then USB blaster. Now with a JTAG ready, double-click in the empty space to add nodes to view in the Logic Analyzer. You choose the list then to see a list of signals, and then you use the arrow in the middle to push signals over from one side to the other, so the signals that are on the right will be the ones that will be analyzed for which data will be collected. This shows the process of adding the signals to be analyzed. As you continue to configure SignalTap II, you need to select which signals to collect Trace Data and which ones to use for triggering in the columns that are on the left, and then over on the right, you want to click next to clock, and then click list and choose from that list to clock that you want to use in order to latch in all the data that you've defined on the left. You have to configure the data, and then you have to configure the clock. Select File, Save, and then name the STP file, STP standing for SignalTap type of file. Then you'll want to go over to the upper left corner and start the rapid recompile, to recompile the design to load the Logic Analyzer into the FPGA. If you don't see the rapid recompile icon, if it's been grayed out, then you can go ahead and do a full compile. It may be that this was the first time the design's been completely compiled, so you want to go ahead and compile it at that point or the rapid recompile actually takes much less time than a full compile, so it's helpful to use that when you can. Then you want to program the device from the SignalTap interface. You're going to load up your FPGA with the existing design that as got the SignalTap internal analyzer built into it. You can do that by pushing the button that's pointed to by the red arrow, and then you want to click the Run Analysis button in the upper left together data, and then they acquired data is displayed as a time waveform. You can also note that at least the number of logic elements and memory bits that are used by the analyzer. The analyzer does need some FPGA fabric, and this is a limitation of the analyzer, you have to understand that if your FPGA design is using all of the FPGA resources, it's completely fall, then there's not going to be room to place this Logic Analyzer so that you can see the internal signals. You're going to have to then reduce the size of your design. Although in most cases, there will be room for this. The analyzer doesn't take up very much space, although that's dependent on how deep you make the memory buffers. If you make the memory buffers very large, then it will tend to take up a lot of memory blocks, but it is configurable. In most cases, you're going to be able to run the analyzer, but you do have to keep in mind as your design gets to be large and almost fills out the part that you might run out of room in order to place the analyzer so you can see the signals that you try to use for debugging. In summary, in this video, you have learned how to use the SignalTap II Internal Logic Analyzer for FPGA hardware debugging, how to analyze signals internal to the FPGA without external probes that may cause signal integrity issues, and how to understand the limitations of internal Logic Analyzers, which requires some FPGA fabric resources.
