Now let's look at LUTS and FPGA architecture. The field programmer gate array or FPGA was invented to provide a general purpose digitalogic device with great flexibility and utility. It has succeeded beyond the inventor's greatest dreams. Here we will learn about the development of the FPGA, how the fundamental logic cells work using lookup tables or LUTS and how routing becomes a bigger factor in performance. With the intent to create a more flexible general purpose logic device, FPGAs were first designed to imitate gate arrays. Integrated circuits with a sea of gates that were connected by added metal layers or wire routing to define the functionality of the device. However, instead of implementing the logic using transistor gates, the logic was in many cases implemented by memory. Fashioned as lookup tables. This demonstrates how the LUT can be used to implement any four-input, one-output logic device. Here note the regular, methodical way that the table is created. A has all 0s and then all 1s. Variable B has four 0s, and then four 1s, etc. Then to create the output F, note that if A and B are true, F is true. This is the last four rows of the table, which implements the top and gate. Also, if C is true and D is not true, then F is true. So given all the possible combinations of the inputs are listed, we can create any logical expression for four inputs by how we program F. These expressions can also be implemented as and/or circuits as shown. Semiconductor companies were good at making memories, which had regular highly optimized structures that were easily replicated. The first FPGAs were an array of logic cells consisting of three input LUTS. FPGA architecture is different from CPLDs, as the logic element is smaller, usually implemented as a LUT. In this example, the microsemi IGLOO VersaTile can be either a three input gate of any type, or a sequential D-flip-flop or a latch. The schematic depicts the structure of the logic element. Each L-labeled switch is controlled by the configuration bits when the FPGA is programmed. Here's a simplified schematic of an FPGA logic cell. A typical cell consists of a 4-input LUT, a full adder, the FA, and a D-type flip-flop. The LUTS in this figure are split into two 3-input LUTS. In normal mode, they're combined into a 4-input LUT through the left mux. In arithmetic mode the outputs are fed to the FA. The selection of the mode is programmed into the middle multiplexer. This is a schematic of the ulterior cyclone logic element, or LE. Inputs are on the left. Outputs are on the right. The core of this LE is a four input LUT, which can be used to create any four input logic combinatorial circuit. The LUT output is part of a carry chain structure. Used to speed up arithmetic computations. The LUT output can be routed out directly or register by the flip-flop. As you can see, this circuit is designed with versatility in mind. The FPGA user could determine the function of small clusters of gates, the logic cell, and how that cluster is connected to other clusters on the chip, gradually building up a circuit by connecting logic cells. However, to implement a high fan-in function like an address decoder, FPGAs need to cascade many stages of logic elements. This can lead to excessive and somewhat unpredictable delays. Timing analyzer tools and the design software help resolve these problems to some extent. The routing in a FPGA is hierarchical, at the lowest level, we have routing switch that is controlled by a bit of SRAM, or a flash bit, or a fuse. There are many routing switches in local routing to connect various logic elements or blocks. The FPGA is made up of a sea of logic blocks. Groups of the blocks are connected by long lines or very long lines. Common signals like clocks are routed on special routing networks called Global Networks. This slide shows the evolution of the FPGA architecture. In 1995, Xilinx made FPGAs with a NxN array of cells with global routing down the center spines. By 2000 they had added block 4k rams. In 2005 multipliers were added along with hard core processors, a power PC in this case. Among the earliest true P sock parts. In 2007 they added the DSP cores. From this evolution it can be seen that FPGAs no longer operate in the realm of glue logic but are becoming subsystems or complete systems in and of themselves. This development is fueled in part by the use of SRAM memory for the routing switches. Which has higher density than EEPROM. Ram processes are the first ones proven in a new semiconductor process geometry, so they have highest density available at the time. The other development was the use of new means of design entry other than Boolean expressions,including schematic entry and HDL languages like Verilog and VHDL. The type of configuration memory used to create routing switches, is the most important aspect in determining differences in performance and capabilities in the FPGAs. Antifuse FPGAs are known for reliability but they are one time programmable and expensive. FLASH FPGAs are also very reliable and there are also re-programmable, but higher price than SRAM FPGAs. SRAM FPGAs are programmable with highest density and lowest cost for equivalent logic. The four major PLD vendors have a variety of offerings that include many configuration types. Xilinx offers FLASH CPLDs and FPGAs and SRAM FPGAs. Altera provides FLASH CPLDs and SRAM FPGAs. Lattice sells SRAM CPLDs and FPGAs. And Microsemi offers Antifuse and FLASH FPGA's. Given all this, why use a CPLD instead of an FPGA? Remember, if you need just a little logic the CPLD can be a less expensive option. It may also allow more IO in the same space with less logic cost. CPLDs may also be the best choice if you have to meet very tight and deterministic timing requirements. In module two, you will learn how to create an FPGA design, using FPGA design tools. The tools we use are process flow like one depicted in the picture. The design begins with design entry, continues to simulation to verify the logic as implemented as expected. And then the tool will perform synthesis, also called mapping, to map the logic to the device architecture. Next, the tool will create the interconnection between the cells by place and routing or fitting the design. It is good practice to run another simulation after the fitting is completed. If this all looks good, the next step is to use the tool to create a programming file, which is then downloaded into the FPGA device for testing. Here's a good free recommended resource for learning about FPGAs, a short book, FPGAs for dudes. In this video, we have learned FPGAs are highly flexible general purpose digital logic devices, due in part to the clever use of memory elements as LUTS for the base logic cell. FPGAs scale better than CPLDs. Creating lower cost solutions for larger designs and designs that require many flip-flops. Because FPG architecture is finer grained than CPLDs, routing has more impact on performance. FPGA configuration memory can be implemented using one of several different technologies, including SRAM, Flash and Antifuse, this choice impacts cost and performance. FPGAs provide a myriad of ways to create your next logic design.