We will mention now, some recent advances in microelectronics processes and their impact on the preparation of high performance solar cells. The first objective is to overcome at least partially, the requirement of epitaxy, that is through the systematic conservation of the lattice parameter, during cell preparation. This will allow the preparation of higher conversion efficiencies with cells consisting of four junctions. Another challenge is obviously, to ensure compatibility between III-V, on silicon technologies in particular, to be able to increase the cell size. This last objective will be limited by the flatness requirement as a molecular level. Let us present here for example, the process, smart cut, developed first at CEA-LETI in grenoble, and then by the speed of soitec. The objective is to obtain from the massive silicon, thin crystalline silicon on an insulator silica. The process starts from two bulk silicon wafers, one of which is thermally oxidized on the left in order to obtain a significant layer of silica. This wafer is exposed to a proton beam, H plus, which will be implanted in order to weaken the crystal lattice on an area close to the oxidized surface. The two wafers, are to be bonded as the molecular level, as will be seen later. After a very accurate cleaning of the surface, the implanted zone is weakened, the wafer will be splitted into two parts, from this implanted area like a cutting on the dotted line, smart cut, is thus obtain a thin silicon layer on top of oxide, which allows the production of devices on insulator, the other part of silicon is recycled. Let us return briefly to the molecular bonding. The goal is to move between two bulk objects, from Van der Valls bonding, relatively weak, towards very strong covalent bonds. The principle of the metal, is illustrated here in the case of two hydrophobic silicon surfaces. We start with a very fine cleaning, as a molecular level of the two surfaces that we will get in touch, then the whole system is heated up to several under degrees under pressure. The surface energy is increased by several orders of magnitude, signature of the bonding at the molecular level. We present here an application of this type of method a cell of gallium arsenide of 10 micrometres thickness, on 25 percent efficiency was transferred onto a flexible metallic substrate, allowing a spread of application on the potential reduction of cost. Let's deal now with quadruple Junction, which aims to increase efficiency at more than 40 percent. The value of the gap as functions of the lattice parameters, are given the left figure. Gallium arsenide and Indium phosphate, display major mismatch in terms of lattice parameter. At constant lattice parameter, InP can be associated with material with narrow gaps, on gallium arsenide to wide gaps. Such structure can be prepare InP on gallium arsenide respectively, as shown here. Then, these two structure are molecularly bonded as shown here. Finally, the gallium arsenide substrate is removed using a microelectronic process, thus obtaining quadruple high performance junction. The molecular bonding can be also used to transfer III-V on silicon cells, as shown here thus, obtaining a triple junction on crystalline silicon. Such quadruple junctions are very small, less than one centimeter square, to meet the surface flatness at the molecular level. Under concentration, it's possible to obtain efficiencies of about 45 percent on absolute record, with the VOC of four volts. Industrial production of a 22 megawatt pick plant is shown here in South Africa. The units cell of very small sizes as soitec safetied, with polymer lens panels, that provides a concentration of the cell lines on each unit cell. These high performance cells based on III-V semiconductor, are shown at the top of this computation from NREL. Remember this regard are obtained in the laboratory condition on small areas. So, 40 percent threshold was achieved in 2010, it is now at the 45 percent level. We just treat crystalline cells and finally, III-V semiconductors, the most powerful ones. We will deal later with other semiconductor materials, not crystalline, but dissolve them on the cells obtained from the combination of crystalline on number four silicon. The so-called, a trio junctions. Thank you.
