[MUSIC] Hello again, I hope you've been learning from the lectures so far. In the recent lectures, you were introduced to the HIT or heterojunction with intrinsic thin layer solar cell structure. This architecture uses hydrogenated, amorphous silicon layers to perform the doping and passivation functions within the solar cell. Let us now consider this design in more detail by working through an example question. The question is stated as follows. HIT cell is constructed with doped layers consisting of amorphous silicon. On the front side, an n-doped amorphous silicon is used. However, no transparent conductive oxide layer is added to perform the lateral current conduction to a busbar. We are to consider it as a rectangular one centimeter squared cell. 10 cm x 1 mm, with a busbar on one edge. So a distance to the bus bar of one millimeter. For this configuration, calculate the series resistance added to the circuit and draw this on a representative IV curve. If you would like, you may stop the video at this point and try to solve the problem on your own. If not, let's proceed together. A diagram of a typical hit cell as presented in the lectures as shown here along with the thicknesses of all the relevant layers. Note that the n-doped layer is indicated as being about 50 nanometers thick and is accompanied by no TCO layer. On the rear face, there is a TCO layer, namely 80 nanometers of indium doped tin oxide, ITO. One piece of information that we are missing is the conductivity of n-doped amorphous silicon. For the best phosphorus doped amorphous silicon, the conductivity or sigma is about 10 to the minus 1 per ohm centimeter. This low value is due to the poor mobility in this semiconductor as well as the fact that not all doped atoms are active in this material. Now let's consider the model case we've constructed. We have a piece of n-doped silicon, which is only 15 nanometers thick. To keep the units consistent, that's 15 x 10 to the -7 centimeters thick. The maximum distance to the busbar is one millimeter and the length of the cell is ten centimeters giving an area of one centimeter squared. We'll assume a worst case scenario and calculate the total resistance that current entering at one edge must patch through to get to the busbar at the other edge. We'll assume that once the carriers get to the busbar, they're essentially out of the cell. So there's no contact resistance between the silicon and the busbar and none within the busbar either. The formula for the resistance of a conducting slab is, L, the length of the slab divided by W, its width. T, its thickness and its conductivity, sigma. If we plug in the numbers for our layer, we get a total resistance of the slab of 67 kiloohms. So is this a large value or a small value for a photovoltaic cell of one centimeter squared? We can get a feeling for this by plotting a model IV curve for an HIT crystal and silicon cell. First we can plot reasonable values for the open circuit voltage VOC and short circuit current ISC. We'll say VOC is 0.7 volts and a really good value of short circuit current density is 40 milliamps per centimeter squared. So for our 1 centimeter squared cell, we'll use 40 miliamps. For an efficient cell, we want a nice square looking IV curve, something like this. We recall that the impact of the series resistance is best seen by the inverse of the slope of the curve at VOC like this. Using the series resistance, we calculated 67 kiloohms, we can use the voltage currant resistance relationship to get the currant that would drop VOC when it's flowing. This gives us the answer of 10 microamperes. 10 microamperes, that's nothing compared to IFC. And so our current voltage curve would look like this at best. In other words, this series resistance is enormous, and there's no way our solar cell could operate correctly if the current was transported laterally this way. That's why we need the TCO in an HIT cell to conduct current laterally to the bus bar. To compare, let's contrast this with the same situation but with a diffused crystalline silicon layer. Here's the calculation we just did for a doped amorphous layer, giving a series resistance of 67 kiloohms. For a crystalline silicon doped layer, a few things change. The thickness of the diffused layer is much greater than in the HIT case, more like four microns. Giving four times 10 to the minus 4 centimeters. Also, the conductivity is 1,000 times higher on the order of 100 inverse ohm centimeters. All this together gives a series resistance of 0.25 ohms. So is this good enough? We can plot this on the same IV curve as before. This time calculating how much voltage is dropped by flowing IST through this resistance. During the calculation, we see that it's only ten millivolts. That's 10 millivolts out of 700 millivolts, so not too bad. It's something that could be improved, but it's not a show stopper, like the case for amorphous silicon. And we definitely don't need the TCO in this case. To summarize, we've shown that although amorphous silicon layers are amazingly effective for passivation and band bending. Their conductivity necessitates the inclusion of a TCO layer to perform lateral conduction, which diffused dope layers do not require. Through this work problem, I hope you've gained some insight into why HIT cells are designed the way they are. Thank you for your attention and see you again soon. [MUSIC]
