So far, we learned the PN junction and metal semiconductor junction. Then now, in this lecture, we are going to learn metal oxide semiconductor capacitor. Once we finished this MOS capacitor, we are ready to learn our final core of the MOSFET. MOS capacitor is showing in here with a metal, and gate dielectric, and semiconductor. This is the MOSFET where the source and drain. So MOSFET device, we can say four-terminal because the gate, source, voltage, and p-type semiconductor potential should be applied. But MOS capacitor, we are only going to learn these red boxes, that metal oxide semiconductor, which is the two-terminal devices. This is the MOS capacitor here, n+ polysilicon, and the gate dielectric, and p-type semiconductor. From n+ source, p-type silicon, and n+ drain, you have a two PN junction: n+ p-n junction, p n+ junction. So here's the n+ semiconductor, and the middle part of the p semiconductor, and n+ semiconductor. So here's the PN junction, PN junction. Here, n+, there are a lot of electron carrier. Below is the fixed charge of the [inaudible] positive charge, and p-type semiconductor, there are a lot of holes majority carrier, and then negative boron charge. Here are n+ again. Then under equilibrium, Fermi energy is constant. Let's look at the MOS region. This is the very short MOSFET device, gate length is around 25-nanometer gate length. Then here is the gate dielectric of the oxide. Polysilicon is actually very highly doped, this is the gate material. So gate and then gate dielectric of silicon oxide, which is the thickness here is 1.6 nanometers. This is the source and drain. Silicon dioxide is amorphous silicon which silicon atom surrounded tetrahedrally by four oxygen atom. Silicon oxide, the distance is normally 0.15 nanometers. Then one silicon oxide layer, you can say between 3-4 [inaudible]. The gate dielectric constant is 3.9, you should remember. Then band energy gap is the nine electron volt, and resistivity is like this. Modern short-channel MOSFET device normally use one nanometer of silicon dioxide gate dielectric. Then how many layer of silicon dioxide is used in one-nanometer silicon oxide? As I said in previously, one layer is 3-4 [inaudible]. So one nanometer is 3-4 layer of dielectric, can totally block the current between the gate polysilicon and p-type semiconductor. It is amazing. This is the real MOS cases, metal oxide and p-type silicon capacitors. If you draw the energy diagram, here's a metal Fermi energy level. The silicon dioxide, band diagram is nine electron volt, and this is the p-type semiconductor. This is the real cases, but if you're making a band diagram of the real MOS capacitor is a very complicate. Let's assume one simple case that metal work function and semiconductor work function is equal. Then we making our band diagram is like these simple cases. Although this doesn't look like realistic, this assumption will simplify our approach. But in another sense, this is also can be possible. As I said in a previous metal to semiconductor contact, I said depending on the metal material, work function of the metal is different by the gold, silver, platinum, etc. So if you can choose some light metal material, then you can choose the metal work function that has equal to the semiconductor work function. Let's assume that Pi ms Pi s, then make our contact of the MOS capacitor on the equilibrium becomes like this. Here's the metal work function and semiconductor work function, band diagram, E_c and E_v located here, and then this is the Fermi energy from the relative to the E_i. Here, we use [inaudible] modified work function definition. We said work function of Fermi energy to the vacuum, but the band gap of the oxide is a huge nine electron volts, so you can think that the band gap of oxide is the work function to the vacuum. Because the work function is the metal in electronic metal to the outside of the vacuum region. So this is the modified work function and modified work function of the semiconductor, so they are the same. This energy band diagram of semiconductor which is the flat when Pi ms equal to Pi s called flat band conditions. We starting from the flat band condition. So most band diagram under bias. Basically, MOS capacitor is basically normal capacitors. Now, if we applying the voltage, there will be charges accumulating outside of dielectric. This is the flat band condition on the equilibrium when you applied zero gate voltage. Now, you applying negative voltage to the gate, what's going to happen? First, you applying negative voltage to the gate, you will increasing the potential of the metal side. Because this is a band diagram based on the electron, the negative voltage, it will be increase the potential of the metal side. Then you will increase the energy band diagram oxide upper to the metal side. Then Fermi energy, since this is the oxide blocking the current flowing between the metal to semiconductor, so Fermi energy doesn't changing for both metal and semiconductor. Since you applied the negative voltage, you expel. The majority electron in inside region makes the space charge of the positive charge of, this is the p-type semiconductor, now, you applying negative voltage the MOS capacitor of the p-type semiconductor. You apply the negative voltage, then you increasing the potential of the metal side to the upper. Because band diagram is based on the electron, applying negative voltage will increase the potential of the metal side. Since you're applying negative voltage, you expelled the majority carrier holes. You attract majority carrier hole to the semiconductor region because you're applying negative voltage. Then there will be majority hole accumulation in p-type semiconductor, the same charge of the opposite negative charging metal is accumulating in this capacitors Also the bend is increasing, so therefore, bend of the silicon oxide is this direction, the slope is negative, therefore, electric field in this slide because this is a negative and this is a positive. Also you need to draw this thing in band diagram because here semiconductor is a 1.1 electron volt and silicon oxide, nine electron volt expressed a huge difference on the bandgap. You expressed this one and then conclusion is that you are applying the negative voltage to the gate. Some electro-potential voltage is consumed in electric field formed in oxide layer. Also some voltage is used to accumulate the majority hole in p-type semiconductor. Since majority holes accumulate at the interface, Fermi energy is close to the E_v near the interface, therefore, band is bending. Also this oxide layer blocking the current between the metal to semiconductor, therefore, Fermi energy in both sides doesn't change. What happen to the positive charge? If you apply positive charge, your doors of the energy level of the metal side downward. Then you apply the positive, then you expel majority holes in p-type region, makes the space negative charge of the bottom. Fermi energy doesn't change and then your door the band diagram oxide go down and then filled the slope of the energy band diagram. Means that there is potential difference by distance, and then this is a positive, therefore, positive electric field form in this direction. Some portion of the positive voltage is used in the electric field in the capacitor and some portion of the positive charge is used in the fixed charge formation in the junction of p-type semiconductor. Since there is space negatively charged at the junction, which means that Fermi energy is close to the E_i near the junction. This condition called depletion in contrast to the majority hole accumulation. What happen to the more positive voltage is apply this condition called inversion. Actually, the MOSFET device is operated in this inversion conditions. If you apply further positive voltage compared to the depletion, then you do all the metal oxide much further the slope of the oxide bandgap is higher, means high electric field. There is still depletion charge at the p-type semiconductor. In addition to the depletion charge and the band is further go down of the E_i, so the Fermi energy is above the E_i. Means there is mobile electron charge. These mobile electron charge is of the minority carrier core inversion charge. Fermi energy at the junction region. Fermi energy above the E_i means there's a electron. Where did this inversion electron came from? They came from the minority carrier of a p-type semiconductor and they apply very high voltage, gate voltage, then minority carrier in p-type semiconductor will go through the depletion region and gathered underneath oxide layer. These mobile inversion minority charge with the driving force of current flowing or not flowing or digital 1 and 0 of the MOSFET transistor. Inversion is most important in here. This band diagram of MOS capacitor is very, very important. Before we go more deeper of understanding each state, I strongly ask you to draw by yourself in next slide. First you draw flip and the condition and you draw the depletion band diagram and inversion band diagram and accumulation band diagram. Without drawing the band diagram by yourself, only listening to my lecture doesn't nearly help you, so draw these graph by yourself in next three minutes. Let's learn each condition of the most capacitor a little different. First accumulation. You are applying negative voltage to the gate, then you increasing the potential metal psi and then since you are applying negative, the majority holes are accumulating in the junction, and then also electric field is slow-paced, negative means electric field in the other side in the oxide layer. Then since there's the majority hole accumulation near the junction, means that Fermi energy is close to the E_v. Since there is no current between metal oxide semiconductor structure, no changing in Fermi energy. Therefore, metal will function and semiconductor will function do not change with the applied voltage. Majority hole accumulation near the silicon surface can be described the vacation with a P equal n_i exponential E_i minus E_f. Since this is very a high value, means there are all that level majority hole near the silicon surface. They're discharged either from the negative charge and positive charge and then relatively high positive charge compared to the neutral charge, neutral p-type [inaudible]. Either case, there's the charge, then there is electric field, and then they'll be gradient of the E_i means the band is bending. Since there is charge electric field, electric field band is bending. Slope of a band is bending is here's the negative, then there is electric field of the negative, and then energy bands of the silicon near the surface go up to express the majority hole accumulation near the oxide silicon interface. Depletion, you are applying positive voltage to the gate, then these doors potential of the metal psi. You expel majority holes in p-type region, majority hole in junction region makes the depletion charge of the proton, negative charge. Since there is no charge in depletion region, Fermi energy is close to the E_i, so band will be bending to downward similar to the metal to p-type silicon contact. Then at the junction area, majority hole is depleted. There is negative depletion charge, which is related with the doping concentration of the acceptor. Space charge can be expressed by the qN_aW because the charge is the constant, because related doping concentration is constant. So space charge is negative because of the proton, and in contrast, the same amount of the positive charge of the metal p-Si. There's charge, then there is potential difference so that the Fermi energy more close to the E_i at the junction area. For the case of the inversion where you are applying very large positive voltage, then you further decrease the potential of the metal p-Si. Then p-type semiconductor go down much further where the Fermi energy is above the E_i. This means that in addition to the depletion charge, there is extra mobile inversion charge at the interface. Where's this inversion charge came from? These inversion electron minority charge came from a p-type semiconductor, and there is a minority electron in neutral region. They gathered underneath the oxide region because of the very high positive voltage into the gate. So this inversion, Fermi energy is lower than E_i. So inversion charge np equal to the n_ie, exponential Fermi energy minus the E_i. This much inversion charge is formed. So at the interface, E_f minus E_i is very high. Therefore, huge minority inversion charge is form much higher than intrinsic carrier concentration, and the embodied layer of huge minority carrier is separate from the majority hole by the depletion region. This is very important to contact. If there are huge minority electron is existing in the oceans of majority hole, those minority carrier can be recombined with the majority carrier and disappear. How come those minority inversion charge can be survive in p-type semiconductor? They can survive because they can separate by the depletion negative charge. Those minority carrier separate by the majority holes by the depletion charges, therefore, minority electron can be survived in MOS inversion cases. This is the key technology to MOS transistor.
