[MUSIC] So let's learn threshold voltage. Threshold voltage here is the same threshold voltage that I told you in the first class of our lectures. I said in most capacitor gate voltage above the threshold the voltage transistor is on current flowing and digital one. If the gate voltage is below the threshold voltage, transistor of current not flowing and digital zero. So threshold voltage is the turning on voltage of the most transistor. So before we learn the threshold concept. So if we applying the gate voltage to the most gate voltage drop as I discussed in previously occurs across the oxide layer and depleting the silicon. So gate voltage apply is consumed in the oxide layer integrated voltage plus depleting the silicon which can be expressed with a surface potential. So from now on, you can be very confused because of the gate voltage is similar to the surface potential. So don't think the surface potential is the gate voltage. They are very similar, but they are not equal. Gate voltage is much larger concept than surface potential. Gate voltage applied and surface potential is increase. However they are not equal, because gate voltage is also consumed in insulator. Also insulator voltage is proportional to the charge between the charge outside of the oxide which called the silicon charge over insulating capacitance. The charge per unit area in silicon area is Q is negative value as we learned in previous lecture. Those negative value is consistent with the depletion charge of the boron in P type semiconductor and audition of the emergent minority electron charge. So they are all negative value, so that's why we put the minus here. So depending on the charge in the silicon area, the voltage of insulator can be defined. So what is the surface potential? Surface potential is the potential at the surface of the silicon relative to the Ei in neutral P type semiconductor and phi F is Fermi energy relative to the Ei. So surface potential is zero means that Venn diagram is flat. Its surface potential is positive voltage Venn diagram of a Ei will go downward. So we define the onset of the strong inversion as below the surface potential should be two phi. Means their surface potential equal to the phi F means this, surface potential of the two phi F is, One, two, therefore this way will be 2 phi F. What is the meaning of the 2 phi F? This 2 phi F meaning that inversion minority carrier should be formed such that it should be equal number of the majority whole in neutral region. So minority inversion charges high enough that, so that those inversion charges comparable to majority whole in neutral region. That's the onset of the strong inversion. This onset of strong inversion is a little complicated, but at the threshold the voltage, current is not flowing. This is the onset of the strong inversion, just above the threshold the voltage current is flowing. So this is the starting point of a current flowing, which is the threshold voltage. Since we define the threshold the voltage of the surface potential is 2 phi F. Then threshold voltage of the gate threshold voltage of gate voltage should be defined that surface potential 2 phi F plus the insulator voltage over this value, negative charge of the neutral region. However, we change it Qs to the Qd. Qs means negative charge of depletion and inversion in P type semiconductor junction area. The Qd is only depletion charge. Why we change the Qs to Qd? Because at the onset of the strong inversion or threshold voltage there are negligible inversion charge. So no, you can think of almost negligible inversion charge then Qs is only depletion charged with no inversion charge. That's why Qs is replaced Qd. To understand this concept more easily, let's look at this Venn diagram. So if you are prime gate voltage below the threshold voltage and above the zero voltage. Then you expel majority carrier whole makes the negative fix charge of the border. Once it reached the threshold voltage or onset of the strong inversion, phi S is 2 phi F. Therefore, Fermi energy is above the Ei. And then, This is important that inversion charger here is exactly same, Charge or charge concentration of the background doping of the P type silicon. So let's say that P type silicon is 10 to the 15. Those inversion charge is 10 to the 15 when phi s reach to the 2 phi F. But in this case, those inversion charges negligible compared to the entire depletion charge. Normally those inversion charges is the less than 10 nanometer in advanced semiconductor, they are two nanometers. So those charges, the totally negligible degrees compared to the space charge, depletion charge in here. So therefore, Qs = Qd. However, if you're increasing the gate voltage, Above the threshold voltage, which means that phi S equal above the 2 phi F then choose the Fermi energy. Fermi energy is much above the Ei choose electron minority carriers are gathered at the inversion layer within the 10 nanometers. Then choose mobile electron inversion charges form that's the driving force of the current flowing in most transistor because the depletion charges non-mobile. They are fixed to charge. These are the moving between the source and rain. So inversion charge. Once the inversion condition reached, then electron concentration near the surface increasing very fast by even the small increasing in the band bending or apply the gate voltage. A little bit of applying gate for the gate voltage increasing huge number of the minority inversion charge. And this condition, W depletion width is maximized because the further gate voltage apply or surface potential increasing, doesn't influence the depletion width. But it's much easier to gather more minority inversion charge here. So slight change in gate voltage should increase inversion charge. Therefore, depletion width is maximized which is the W max. So what is the inversion charge in silicon area which is the Qs. Qs is, as you can see here in P type semiconductor is the all negative, of depletion charge of negative and inversion charge of the negative. So Qs of the semiconductor charge is negative consistent with the negative inversion charge with minus the depression qNa doping concentration W max is all three positive. Therefore you put the negative one. So therefore Qs is the negative which is equal to minus metal side charge, Qm metal side charge is the positive. Therefore, you put minus Qm which is, this is the negative charge. So do you know the p junction W is like this and then this is the n + p junction. Therefore, Nd is deleted because very high doping concentration. So W becomes like this, and this is the built in potential is 2 phi F. And the surface potential after the onset of the threshold voltage, W is maximized. Therefore, surface potential should be 2 phi F after 2 phi F, the W is saturated. So W doesn't changing, so we put 2 phi F like this, and final is like this. So Qd over depression charge is qNa W max. If you insert W here, final result is like this. So this graph is very interesting. So this is the charge of the silicon, Qs. Charge of the silicon Qs versus surface potential. To understand this, you shouldn't confuse this surface potential with gate voltage. Surface potentials strongly related the gate voltage, but the gate voltage not only influencing the surface potential they used in the insulator voltage. So if you apply high gate voltage you have a high surface potential but the surface potential is not equal to the gate voltage. So what is the meaning of the surface potential is the 0? 0 means that right? Now you are applying positives of this surface potential means this go over. Means their EI crossed the Fermi energy means there is the depletion of a major carrier whole. And then further in phi F region means there, in phi F is this. This phi F is the depletion of all the phi F, Then there is a slight weak inversion, slight weak inversion has occur. Slight minority carrier electron is gather, but they are extremely negligible compared to the background P type concentration. Let's say that their background is 10 to the 15 and minority gather these the 10 to the 10 negligible. And 2 phi F inversion minority carrier is comparable to the P type region that is the onset of the threshold voltage or strong inversion. And then at 2 phi F, W is maximized and further our prime gate voltage is exponentially increasing inversion charge. If you apply negative voltage and negative surface potential, then exponential whole accumulation is occur. So a little summary of the inversion. As I said, inversion layer is less than 10 nanometer in advance semiconductor, so almost 2 nanometers. Therefore, we can neglect those with when we drawing the electric field distribution. So here's the inversion Venn diagram and then positive charging mirror side and then depletion charge and the inversion charge. Or our negative there is a charge and there is electric field by the process equation and the electric field in constant in oxide layer. And then those electric field is not drawn here because we can neglect them. And then electric field is showing in here, integration of electric field is electrostatic potential which is the opposite to the Venn diagram. As you can see, apply the gate voltage is used in the insulator and surface potential difference. Apply the gate voltage is used in insulator voltage and surface potential. Qm, which is the positive charge is minus Qs and the silicon charge in P type region, which is negative. So this is the negative, this is the positive, we put the negative value here. Then qNa W max minus inversion charge Qn is the negative. So negative to the negative is a positive. And then gate voltage is used in the insulator and surface potential and then insulator voltage is minus silicon charge over the capacitance of the insulator. And onset of the threshold voltage, onset of the strong inversion, there is no inversion charge. There is no negligible charge, so silicon charge is equal to the Qd. So threshold the voltage is minus Qd over insulator capacitance plus 2 phi F because the onset of threshold voltage, surface potential is 2 phi F.