You should complete the VLSI CAD Part I: Logic course before beginning this course. A modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing. Recommended Background: Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Elementary knowledge of RC linear circuits (at the level of an introductory physics class).
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From the course by University of Illinois at Urbana-Champaign
VLSI CAD Part II: Layout
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From the lesson
Timing Analysis
You synthesized it. You mapped it. You placed it. You routed it. Now what? HOW FAST DOES IT GO? Oh, we need some new models, to talk about how TIMING works. Delay through logic gates and big networks of gates. New numbers to understand: ATs, RATs, SLACKS, etc. And some electrical details (minimal) to figure out how delays happen through the physical geometry of physical routed wires. All together this is the stuff of Static Timing Analysis (STA), which is a huge and important final "sign off" step in real ASIC design.
Meet the Instructors
Rob A. RutenbarAdjunct Professor
Department of Computer Science
So here we are in lecture twelve. And we're going to talk about timing.
So where are we in the, the CAD flow? You synthesized it, you got 10 million
gates, you mapped it. You got 10 million or so gates from the
available technology library. You placed it, so you know where they are
on the surface of a piece of silicon that's maybe you know, a centimeter on a
side. You routed it.
So you got 10 or 20 million wires across 10 layers of metal connecting everything.
What's the next question you might want to ask?
And the question is, how fast does it go? Right, doesn't meet the timing
requirements when I started the design. Let's assume, for example, that I want it
to run with a 1 gigahertz clock. Then, I've got 1 nanosecond in which to
get all the work done. So, everything that comes out of a
storage element and goes through a big blob of logic, and goes into another
storage element. All that stuff's gotta happen in 1
nanosecond, in 1,000 pecoseconds. How do I tell if that's possible?
How do I look at the logic and see if I'm doing it right?
How do I model the physical delay, the electrical delay of the wires that we
spent all that time learning how to route that connect all the logic elements so
that I know that all those paths through the gates and through the wires are
actually meeting all of my timing goals. And even beyond that, if I'm not meeting
my timing goals where do I look to figure out what went wrong?
What are the most problematic things that I might be able to go back and fix?
This is the universe of timing. And so, in this introductory lecture
we're going to talk about what we're going to do on the logic side and what
we're going to do on the layout side as we go forth to explore timing, so let's
go take a look. So, our new problem is to talk about
timing. to date, in all of the material we've
done in the class, we've basically focused pretty much on function, logic
side function. You know, getting the right logical
function. Being able to verify that it does the
right thing as a, as a boolean equation or a, or a network of gates.
Optimizing it, you know, reducing the complexity on the physical side, on the
geometry side, making sure we put all the gates some place.
That we optimize things like the length of the wires.
That we correctly do things like route the wires.
you know, it's clear that there are some really deep interactions between say the
logic synthesis and the layout. So, I mean if you just think about the
diagram on this slide. You know, we start with some kind of a
high-level description. And clearly there's something about
timing going on in there. We have not had time in the course to
actually talk about how one deals with time in the earlier stages.
Logic synthesis gives us connected cells with delay constraints on the signal
paths. The physical design, after the very
least, it places the cells in a way that makes them routeable later on.
And then it actually routes them, you know, with connecting wires.
what we're going to focus on here is how one asks questions about the timing
behavior. You know, how fast can this thing go?
And there's some important facts. the logic-side tools have to be able to
estimate the delays through unplaced and unrouted logic.
So it's often the case that they're going to be using very crude models of
what's happening with respect to the geometry aspects of the design.
but once you actually have layout or even rough or approximate layout you can
actually estimate the delays through not only the logic but also some models of of
the wires that that connect them. And so for both the logic-side and the,
and the physical-side, being able to ask questions of timing is really a very
important thing. So our topics for talking about ASIC
timing. Well, we're going to talk about the logic
side of this and so we're going to do some thing that's very important which is
called static timing analysis. And we're going to explain in a while why
it's called static. but for now, the question is sort of
simple. How do we estimate the worst case timing
through a logic network? So we have a bunch of gates and we have a
bunch of wires and, you know, maybe we don't have yet good models of what the
wires are doing in terms of delay. Maybe we have only rough models.
Nevertheless, I've got millions and millions of gates.
I need to be able to ask questions like how fast can it go?
And on the layout side we're going to be primarily focusing on interconnect delay
analysis. So we place the gates, we route the wires
that connect the gates. How do you estimate the delays on the
wires? Because in a, in a modern nano-scale
technology with a chip that's, you know, a centimeter or two centimeters on a
side, millions and millions and millions of gates, you can have an awful lot of
the delay of the logic circuit itself just in the signal propagation through
the physical electric circuits that are the, represented by the wires.
So we've gotta actually be able to ask and answer both the logic side timing
question and the layout side timing question.
So on the logic side, what's interesting is that all the problems look like either
longest or shortest paths through a graph that properly models the gates and if you
do it correctly you can also model the wires.
When we start we won't be modeling the wires but we'll, we'll, we'll close that
loop when we get to the end of the lecture and we'll show you how the
understanding of what the wires do can be incorporated back into the logic-side
analysis. What's kind of surprising here is that
the maze routing idea reappears in a very nice, in a very organic way.
We're going to be talking about wave fronts.
We're going to be talking about expanding.
We're going to be talking about reaching. We're going to be talking about heat.
The very pretty, nice classical kind of a connection from something on the physical
side to something on the, on the logical and the timing side.
And, when we talk about the layout-side and we talk about interconnect delay
analysis, there is no way around the fact that the problem has to be modelled as an
electrical circuit. Now if everybody in the class had an
electrical engineering background we could actually do some cool circuits.
But since I don't think everybody in the class has an electrical engineering
background, I'm simply not going to do the circuit.
So I'm going to talk a little bit about circuit elements at the level of the
basic sort of physics class that I'm assuming everybody has taken, but you
don't really need to know any detailed circuits.
We're going to surprisingly turn all of this stuff into just another
computational task. And I know you're tired of me saying
this, but amazingly enough it's going to be another attractive, simple
computational walk on another special tree data structure.
And by starting from the physical geometry of the wire, turning it into a
special tree data structure, doing a very simple computation that walks the tree,
I'm going to be able to get a surprisingly accurate electrical kind of
a model of the delay of a form that I can actually use for the logic-site timing.
So, it's a very nice way to, sort of, close things in the class with something
that's linking the physical side, the geometry side in a very important and key
way back into the logical side of things. So, with that let's go start talking
about timing, and we're going to start by talking about the logical side of the
world.
[SOUND]
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