Name: VLSI CAD Part II: Layout
Brand: University of Illinois Urbana-Champaign
Availability: OnlineOnly
Rating: 4.7 (55 reviews)

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Learner Reviews & Feedback for VLSI CAD Part II: Layout by University of Illinois Urbana-Champaign

4.7

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282 ratings

About the Course

You should complete the VLSI CAD Part I: Logic course before beginning this course. A modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing. Recommended Background: Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Elementary knowledge of RC linear circuits (at the level of an introductory physics class)....

Top reviews

Jun 18, 2020

Great great great course. Highly recommended for people interested in VLSI CAD design.

Jul 13, 2021

Very well curated course! It is exhaustive in terms of the invigorating assignments and the lucid explanations help satiate the curiosity about the journey from Logic->Layout in VLSI.

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