This comprehensive course bridges the gap between software and hardware by exploring the fundamental architecture of computing systems through the lens of MIPS (Microprocessor without Interlocked Pipeline Stages). You'll master both theoretical concepts and practical skills essential for understanding how processors execute instructions and how architectural decisions impact performance.

MIPS Computer Architecture and Performance Optimization

MIPS Computer Architecture and Performance Optimization

Instructor: BITS Pilani Instructors Group
Access provided by Pak Portal 25
Recommended experience
Recommended experience
Intermediate level
Basic digital logic, programming concepts, and computer organization principles are recommended. No MIPS or assembly language experience is needed.
Recommended experience
Recommended experience
Intermediate level
Basic digital logic, programming concepts, and computer organization principles are recommended. No MIPS or assembly language experience is needed.
What you'll learn
Evaluate and enhance computer system performance using industry-standard metrics.
Develop proficiency in MIPS ISA, including ALU and register file design for optimal performance.
Design efficient single-cycle, multi-cycle, and pipelined processors to maximize computing power.
Implement and optimize cache memory, understanding its impact on overall system performance.
Details to know

Add to your LinkedIn profile
93 assignments
See how employees at top companies are mastering in-demand skills

There are 10 modules in this course
Learn key performance metrics, Amdahl's law, and benchmarking techniques to evaluate computing systems.
What's included
9 videos3 readings7 assignments
9 videos• Total 48 minutes
- Course Introduction Video• 1 minute
- Meet your Instructor: Prof. Virendra Shekhawat• 1 minute
- Meet your Instructor: Prof. Sudeept Mohan• 1 minute
- Defining Computer Performance: Performance Equations • 11 minutes
- Defining Computer Performance Using Instruction Performance • 8 minutes
- Understanding Program Performance • 3 minutes
- Understanding Performance Using Million Instructions Per Second (MIPS) Rate • 7 minutes
- Computer Performance Enhancement Rule: Amdahl’s Law • 8 minutes
- Standard Performance Evaluation Corporation (SPEC) Benchmarks • 8 minutes
3 readings• Total 30 minutes
- Course Overview and Information• 10 minutes
- Computer System Performance• 10 minutes
- Computer Architectures and Layered View of a Computing System• 10 minutes
7 assignments• Total 48 minutes
- Test Yourself: Computer System Performance and Its Measurement• 12 minutes
- Practice Quiz: Defining Computer Performance: Performance Equations • 6 minutes
- Practice Quiz: Defining Computer Performance using Instruction Performance• 6 minutes
- Practice Quiz: Understanding Program Performance• 9 minutes
- Practice Quiz: Understanding Performance Using Million Instructions Per Second (MIPS) Rate • 3 minutes
- Practice Quiz: Computer Performance Enhancement Rule: Amdahl’s Law • 6 minutes
- Practice Quiz: Standard Performance Evaluation Corporation (SPEC) Benchmarks • 6 minutes
Master the MIPS architecture's instruction formats, addressing modes, and register file structure.
What's included
11 videos4 readings12 assignments1 discussion prompt
11 videos• Total 75 minutes
- R-Type Instructions and Register File • 8 minutes
- Memory Organization and I-Type (Load/Store) Instructions• 6 minutes
- Branch and Jump (J-Type) Instructions• 5 minutes
- MIPS Addressing Modes• 2 minutes
- MIPS Instructions: shift, and, or, not, slt, addi, and or• 8 minutes
- Multiply and Divide Instructions: Part I• 7 minutes
- Multiply and Divide Instructions: Part II• 5 minutes
- Floating Point Representation• 20 minutes
- Floating Point Addition • 7 minutes
- Guard and Round Bits in Floating Point Arithmetic• 7 minutes
- Floating Point Computation Capability in MIPS• 2 minutes
4 readings• Total 40 minutes
- Computer Instructions: MIPS Is an Example• 10 minutes
- Computer Operations and Operands• 10 minutes
- Arithmetic Operations• 10 minutes
- Floating Point Numbers• 10 minutes
12 assignments• Total 69 minutes
- Test Yourself: MIPS Instruction Set Architecture (ISA)• 18 minutes
- Practice Quiz: R-Type Instructions and Register File• 6 minutes
- Practice Quiz: Memory Organization and I-Type (Load/Store) Instructions• 3 minutes
- Practice Quiz: J-Type Instructions: Branch and Jump• 6 minutes
- Practice Quiz: MIPS Addressing Modes• 6 minutes
- Practice Quiz: MIPS Instructions: shift, and, or, not, slt, addi, and or• 6 minutes
- Practice Quiz: Multiply and Divide Instructions: Part I• 3 minutes
- Practice Quiz: Multiply and Divide Instructions: Part II• 3 minutes
- Practice Quiz: Floating Point Representation• 6 minutes
- Practice Quiz: Floating Point Addition• 3 minutes
- Practice Quiz: Guard and Round Bits in Floating Point Arithmetic• 6 minutes
- Practice Quiz: Floating Point Computation Capability in MIPS• 3 minutes
1 discussion prompt• Total 20 minutes
- MIPS Instruction Set Architecture (ISA)• 20 minutes
Design arithmetic logic units (ALU) and register files that form the core of MIPS processors.
What's included
5 videos2 readings6 assignments1 discussion prompt
5 videos• Total 39 minutes
- ALU Design with AND, OR, ADD, and SUB Instruction Execution Capability • 14 minutes
- ALU Design with SLT and BEQ Instruction Execution Capability: Part I • 8 minutes
- ALU Design with SLT and BEQ Instruction Execution Capability: Part II • 7 minutes
- Hardware for Reading the Register File• 4 minutes
- Hardware for Writing to Register File • 6 minutes
2 readings• Total 20 minutes
- Designing ALU• 10 minutes
- Designing Register File• 10 minutes
6 assignments• Total 24 minutes
- Test Yourself: MIPS Processor• 9 minutes
- Practice Quiz: ALU Design with AND, OR, ADD, and SUB Instruction Execution Capability • 3 minutes
- Practice Quiz: ALU Design with SLT and BEQ Instruction Execution Capability: Part I • 3 minutes
- Practice Quiz: ALU Design with SLT and BEQ Instruction Execution Capability: Part II • 3 minutes
- Practice Quiz: Hardware for Reading the Register File • 3 minutes
- Practice Quiz: Hardware for Writing to Register File • 3 minutes
1 discussion prompt• Total 20 minutes
- MIPS Processor• 20 minutes
Create a complete datapath and control unit for executing MIPS instructions in a single cycle.
What's included
8 videos3 readings9 assignments1 discussion prompt
8 videos• Total 56 minutes
- Single Cycle Datapath Design for R-Type Instructions • 5 minutes
- Single Cycle Datapath for Memory Instructions: SW and LW • 3 minutes
- Single-Cycle Datapath Design for Branch Instructions• 4 minutes
- Developing Complete Datapath for Single Cycle MIPS Processor• 11 minutes
- ALU Controller• 7 minutes
- Main Controller: Part I• 8 minutes
- Main Controller: Part II • 13 minutes
- Adding New Instructions to the Datapath • 5 minutes
3 readings• Total 30 minutes
- Datapath Design• 10 minutes
- Combinational Control for ALU• 10 minutes
- Combinational Control for Main Controller• 10 minutes
9 assignments• Total 45 minutes
- Test Yourself: Single-Cycle Datapath and Control Design• 21 minutes
- Practice Quiz: Single Cycle Datapath for R-Type Instructions• 3 minutes
- Practice Quiz: Single Cycle Datapath for Memory Instructions: SW and LW • 3 minutes
- Practice Quiz: Single Cycle Datapath Design for Branch Instructions• 3 minutes
- Practice Quiz: Developing Complete Datapath for Single Cycle MIPS Processor• 3 minutes
- Practice Quiz: ALU Controller• 3 minutes
- Practice Quiz: Main Controller: Part I • 3 minutes
- Practice Quiz: Main Controller: Part II • 3 minutes
- Practice Quiz: Adding New Instructions to the Datapath• 3 minutes
1 discussion prompt• Total 20 minutes
- Single-Cycle Datapath and Control Design• 20 minutes
Break instructions into multiple steps to optimize hardware utilization through multi-cycle execution.
What's included
10 videos3 readings11 assignments1 discussion prompt
10 videos• Total 137 minutes
- Introduction to Multi-Cycle Architecture • 17 minutes
- Multi-Cycle Datapath for ADD, LW, and SW Instructions• 19 minutes
- Multi-Cycle Datapath for BEQ and J Instructions • 11 minutes
- Execution State Diagram• 19 minutes
- Identifying the Control Signals • 15 minutes
- State Diagram and Building the Controller: Part I • 9 minutes
- State Diagram and Building the Controller: Part II • 11 minutes
- Introduction to ROM-Based Control Implementation • 12 minutes
- Control Microprogram• 13 minutes
- Microprogram Implementation • 11 minutes
3 readings• Total 30 minutes
- Multi-Cycle Datapath• 10 minutes
- Multi-Cycle Control• 10 minutes
- ROM Based Control and Control Microprogram• 10 minutes
11 assignments• Total 51 minutes
- Test Yourself: Multi-Cycle Datapath and Control Design• 15 minutes
- Practice Quiz: Introduction to Multi-Cycle Architecture• 3 minutes
- Practice Quiz: Multi-Cycle Datapath for ADD, LW, and SW Instructions • 3 minutes
- Practice Quiz: Multi-Cycle Datapath for BEQ and J Instructions • 3 minutes
- Practice Quiz: Execution State Diagram• 6 minutes
- Practice Quiz: Identifying the Control Signals • 3 minutes
- Practice Quiz: State Diagram and Building the Controller: Part I • 3 minutes
- Practice Quiz: State Diagram and Building the Controller: Part II• 3 minutes
- Practice Quiz: Introduction to ROM-Based Control Implementation • 3 minutes
- Practice Quiz: Control Microprogram• 3 minutes
- Practice Quiz: Microprogram Implementation • 6 minutes
1 discussion prompt• Total 20 minutes
- Multi-Cycle Datapath and Control• 20 minutes
Implement instruction pipelining to significantly enhance processor throughput and performance.
What's included
10 videos3 readings11 assignments1 discussion prompt
10 videos• Total 138 minutes
- Video 1: Introduction to Pipelining • 12 minutes
- Pipeline Datapath Design • 17 minutes
- Step-by-Step Execution of an Instruction in Pipelining • 15 minutes
- Graphical Representation of Pipelining Datapath• 16 minutes
- Introduction to Pipeline Control • 13 minutes
- Pipeline Control Signals and Pipeline Control Implementation• 11 minutes
- Step-by-Step Execution of an Instruction in Pipelining with Control Signals • 11 minutes
- Structural Hazard • 11 minutes
- Control Hazard • 13 minutes
- Data Hazard • 18 minutes
3 readings• Total 30 minutes
- Pipeline Datapath• 10 minutes
- Pipelining Control• 10 minutes
- Pipelining Hazards• 10 minutes
11 assignments• Total 45 minutes
- Test Yourself: MIPS Pipeline Architecture• 15 minutes
- Practice Quiz: Introduction to Pipelining • 3 minutes
- Practice Quiz: Pipeline Datapath Design • 3 minutes
- Practice Quiz: Step-by-Step Execution of an Instruction in Pipelining• 3 minutes
- Practice Quiz: Graphical Representation of Pipelining Datapath • 3 minutes
- Practice Quiz: Introduction to Pipeline Control • 3 minutes
- Practice Quiz: Pipeline Control Signals and Pipeline Control Implementation • 3 minutes
- Practice Quiz: Step-by-Step Execution of an Instruction in Pipelining with Control Signals • 3 minutes
- Practice Quiz: Structural Hazard • 3 minutes
- Practice Quiz: Control Hazard• 3 minutes
- Practice Quiz: Data Hazard• 3 minutes
1 discussion prompt• Total 20 minutes
- MIPS Pipeline Architecture• 20 minutes
Master techniques to resolve pipeline hazards through forwarding, stalling, and branch prediction.
What's included
12 videos3 readings12 assignments1 discussion prompt
12 videos• Total 163 minutes
- Data Forwarding Example Using ADD-ADD Instructions: Part I • 20 minutes
- Data Forwarding Example Using ADD-ADD Instructions: Part II• 9 minutes
- Data Forwarding Example Using LW-ADD Instructions • 10 minutes
- Mechanics of Stalling the Pipeline • 12 minutes
- Reducing Pipeline Stalls by Reordering of Instructions • 8 minutes
- Reducing Impact of Control Hazards• 19 minutes
- Delayed Branch Techniques• 10 minutes
- Exception Handling in Pipeline• 11 minutes
- 1-Bit Branch Predictor • 12 minutes
- 2-Bit Branch Predictor • 12 minutes
- Correlating Predictors • 19 minutes
- Tournament Predictors • 21 minutes
3 readings• Total 30 minutes
- Handling Data Hazards • 10 minutes
- Control Hazards and Exception Handling • 10 minutes
- Dynamic Branch Prediction• 10 minutes
12 assignments• Total 51 minutes
- Test Yourself: Handling Data and Control Hazards• 18 minutes
- Practice Quiz: Data Forwarding Example Using ADD-ADD Instructions• 3 minutes
- Practice Quiz: Data Forwarding Example Using LW-ADD Instructions • 3 minutes
- Practice Quiz: Mechanics of Stalling the Pipeline • 3 minutes
- Practice Quiz: Reducing Pipeline Stalls by Reordering of Instructions • 3 minutes
- Practice Quiz: Reducing Impact of Control Hazards• 3 minutes
- Practice Quiz: Delayed Branch Techniques• 3 minutes
- Practice Quiz: Exception Handling in Pipeline • 3 minutes
- Practice Quiz: 1-Bit Branch Predictor • 3 minutes
- Practice Quiz: 2-Bit Branch Predictor • 3 minutes
- Practice Quiz: Correlating Predictors • 3 minutes
- Practice Quiz: Tournament Predictors • 3 minutes
1 discussion prompt• Total 20 minutes
- Handling Data and Control Hazards in Pipeline Datapath• 20 minutes
Explore how different memory types and organization impact system performance.
What's included
9 videos3 readings10 assignments1 discussion prompt
9 videos• Total 114 minutes
- Memory Technologies • 17 minutes
- Exploiting Memory Hierarchy in Computing Systems • 9 minutes
- Introduction to Cache Memory and Locality of References • 12 minutes
- Direct Cache Mapping • 24 minutes
- Fully Associative Mapping • 9 minutes
- Set Associative Mapping • 14 minutes
- Use of Write Back to Improve Performance • 10 minutes
- Cache Controller Implementation • 10 minutes
- FSM for Cache Controller • 9 minutes
3 readings• Total 30 minutes
- Memory Hierarchy • 10 minutes
- Cache Mapping• 10 minutes
- Cache Controller• 10 minutes
10 assignments• Total 39 minutes
- Test Yourself: Memory Hierarchy in Computing Systems• 12 minutes
- Practice Quiz: Memory Technologies • 3 minutes
- Practice Quiz: Exploiting Memory Hierarchy in Computing Systems • 3 minutes
- Practice Quiz: Introduction to Cache Memory and Locality of References • 3 minutes
- Practice Quiz: Direct Cache Mapping • 3 minutes
- Practice Quiz: Fully Associative Mapping • 3 minutes
- Practice Quiz: Set Associative Mapping • 3 minutes
- Practice Quiz: Use of Write Back to Improve Performance • 3 minutes
- Practice Quiz: Cache Controller Implementation • 3 minutes
- Practice Quiz: FSM for Cache Controller • 3 minutes
1 discussion prompt• Total 20 minutes
- Memory Hierarchy in Computing Systems• 20 minutes
Analyze and enhance cache memory performance through optimized designs.
What's included
7 videos2 readings8 assignments1 discussion prompt
7 videos• Total 98 minutes
- Cache Performance Metrics: Hit Rate, Miss Rate, and Miss Penalty• 13 minutes
- Impact of Increasing Block Size on Performance • 14 minutes
- Impact of Increasing Associativity on Performance • 16 minutes
- Improvement in Performance Using Multilevel Cache • 15 minutes
- Victim Cache• 12 minutes
- Why Do We Require Cache Coherence?• 14 minutes
- Snooping Protocols• 15 minutes
2 readings• Total 20 minutes
- Cache Performance• 10 minutes
- Cache Coherence• 10 minutes
8 assignments• Total 36 minutes
- Test Yourself: Cache Performance Measurement and Improvement• 15 minutes
- Practice Quiz: Cache Performance Metrics: Hit Rate, Miss Rate, and Miss Penalty • 3 minutes
- Practice Quiz: Impact of Increasing Block Size on Performance • 3 minutes
- Practice Quiz: Impact of Increasing Associativity on Performance • 3 minutes
- Practice Quiz: Improvement in Performance Using Multilevel Cache • 3 minutes
- Practice Quiz: Victim Cache • 3 minutes
- Practice Quiz: Why Do We Require Cache Coherence?• 3 minutes
- Practice Quiz: Snooping Protocols• 3 minutes
1 discussion prompt• Total 20 minutes
- Cache Performance Measurement and Improvement• 20 minutes
Understand hard disk and SSD storage organization to improve data access performance.
What's included
6 videos3 readings7 assignments
6 videos• Total 44 minutes
- Hard Disk Drive Structure• 7 minutes
- Hard Disk Drive Performance• 6 minutes
- RAID Levels 0 and 1 • 7 minutes
- RAID Levels 4, 5, and 6 • 9 minutes
- Combining RAID Levels• 8 minutes
- Solid State Storage• 6 minutes
3 readings• Total 75 minutes
- Hard Disk Drive (HDD)• 30 minutes
- Redundant Arrays of Inexpensive Disks• 30 minutes
- Anatomy of a Solid-State Drive• 15 minutes
7 assignments• Total 33 minutes
- Test Yourself: Secondary Storage• 15 minutes
- Practice Quiz: Hard Disk Drive Structure• 3 minutes
- Practice Quiz: Hard Disk Drive Performance• 3 minutes
- Practice Quiz: RAID Levels 0 and 1 • 3 minutes
- Practice Quiz: RAID Levels 4, 5, and 6 • 3 minutes
- Practice Quiz: Combining RAID Levels • 3 minutes
- Practice Quiz: Solid State Storage• 3 minutes
Instructor

Offered by

Offered by

Birla Institute of Technology & Science, Pilani (BITS Pilani) is one of only ten private universities in India to be recognised as an Institute of Eminence by the Ministry of Human Resource Development, Government of India. It has been consistently ranked high by both governmental and private ranking agencies for its innovative processes and capabilities that have enabled it to impart quality education and emerge as the best private science and engineering institute in India. BITS Pilani has four international campuses in Pilani, Goa, Hyderabad, and Dubai, and has been offering bachelor's, master’s, and certificate programmes for over 58 years, helping to launch the careers for over 1,00,000 professionals.
Why people choose Coursera for their career

Felipe M.

Jennifer J.

Larry W.

Chaitanya A.
Explore more from Computer Science

Course

Course
IInternational Institute of Information Technology, Hyderabad
Course
UUniversity of Colorado Boulder
Course