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Learner Reviews & Feedback for Hardware Description Languages for FPGA Design by University of Colorado Boulder

356 ratings
96 reviews

About the Course

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....

Top reviews

Jun 4, 2020

This is very good course , but i found some little missing details related to reading materials .\n\nBut this was really very helpful course for me as fresher .

Oct 6, 2020

I think this is a good start in learning how to write VHDL and Verilog.\n\nI would like to see a next level course or recommendations for further writing code.

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76 - 97 of 97 Reviews for Hardware Description Languages for FPGA Design


May 14, 2020

this course is given good idea of Hardware Description Language and i understood the concepts well.

By Muhammad Z Y

Apr 7, 2020

Course content is moderate. But also have complexity level higher for a beginner.

By Uzair A

Oct 9, 2020

its a very nice course. Its help me a lot to understand the basic of fpga.

By Apoorva S

May 25, 2020

A very engaging course to do for beginners having fundamentals strong.

By Yuvraj S R

May 18, 2020

Explanations are not that good for some circuits like memory

By Sourav N

Sep 18, 2020

There should have been more examples of problems.


Apr 30, 2020

a big thank you to all the professiors

By Prakash K R

Jun 24, 2020

It should be more elaborative


Jun 7, 2020


By J S

Aug 5, 2020


By Islam E

May 31, 2020

this course need a person who knows before the basics of both VHDL/Verilog. because i know some basics of VHDL i understood its part but verilog was a little bit hard to me to understand it

By V S V

Sep 29, 2020

Videos could be better, felt it was too fast and didn't cover the concepts well enough

By Harsh A

Jun 15, 2020

Verilog part is explained very well but VHDL part completely unsatisfied.

By Sachin A

Apr 21, 2020

Very introductory. Verilog and VHDL exercises are copied.

By Sakshat R

May 28, 2020

Innovative teaching, but very poor assignments

By Samuel C

Aug 14, 2020

A decent introduction to HDL.

By Pushkar A

Sep 30, 2020

Teaching could be better.

By Eddy Z

Feb 12, 2021

Instruction is somewhat unclear. The instructors just read through example code but fail to adequately explain how the Verilog and VHDL languages actually work. I learned most of that from a separate textbook. Homework assignments' instructions are often lacking in specificity, forcing students to make assumptions.

By Rishi D

Jun 12, 2020

teacher as well as way of teaching is not good . assignments are great though

By Ethan R

Apr 11, 2020

The highlight of this course was the recommended reading materials.

By Surabhi M

Nov 8, 2020

not clear.

By saikumar s

Oct 31, 2020

There is no technical support