This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
Hardware Description Languages for FPGA Design
University of Colorado BoulderAbout this Course
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Intermediate Level
Approx. 36 hours to complete
English
Subtitles: English
Skills you will gain
Writing Code in VerilogSimulating FPGA DesignsDesigning FPGA LogicDesigning Test BenchesWriting code in VHDL
Shareable Certificate
Earn a Certificate upon completion
100% online
Start instantly and learn at your own schedule.
Flexible deadlines
Reset deadlines in accordance to your schedule.
Intermediate Level
Approx. 36 hours to complete
English
Subtitles: English
Offered by
University of Colorado Boulder
CU-Boulder is a dynamic community of scholars and learners on one of the most spectacular college campuses in the country. As one of 34 U.S. public institutions in the prestigious Association of American Universities (AAU), we have a proud tradition of academic excellence, with five Nobel laureates and more than 50 members of prestigious academic academies.
Start working towards your Master's degree
This course is part of the 100% online Master of Science in Electrical Engineering from University of Colorado Boulder.
If you are admitted to the full program, your courses count towards your degree learning.
Syllabus - What you will learn from this course
8 hours to complete
Basics of VHDL
This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.
8 hours to complete
10 videos (Total 48 min), 2 readings, 6 quizzes
10 videos
Why Learn VHDL?1m
FPGA Design Flow3m
Intro to VHDL: Finite State Machine3m
How to speak VHDL, first phrases6m
VHDL Assignments, Operators, Types3m
VHDL Rules and Syntax, Interface Ports3m
VHDL in ModelSim: Download and Install3m
VHDL in ModelSim: Adding to your Toolkit6m
Submitting VHDL Programming Assignments11m
2 readings
Misson 2-001: Week 1 Readings2h
Files for Week 1 Programming Assignments10m
2 practice exercises
VHDL Find the Code Errors30m
Module 1 Quiz30m
12 hours to complete
VHDL Logic Design Techniques
In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.
12 hours to complete
10 videos (Total 52 min), 2 readings, 6 quizzes
10 videos
Combinatorial Circuits4m
Synchronous Logic: Latches and Flip Flops4m
Synchronous Logic: Counters and Registers6m
Buses and Tristate Buffers3m
Modular Designs: Components, Generate and Loops in VHDL3m
Test Benches in VHDL: Combinatorial8m
Test Benches in VHDL: Synchronous5m
Memory in VHDL7m
Finite State Machines in VHDL8m
2 readings
Week 2 Readings2h
Files for Week 2 Programming Assignments10m
1 practice exercise
Module 2 Quiz30m
7 hours to complete
Basics of Verilog
This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.
7 hours to complete
9 videos (Total 92 min), 2 readings, 6 quizzes
9 videos
Your First Verilog phrase11m
Verilog Rules and Syntax; Keywords and Identifiers; Sigasi/Quartus editing12m
Verilog Statements and Operators16m
Verilog Modules, Port Modes and Data Types10m
Verilog Structure10m
Testing with ModelSim5m
Verilog Evaluation11m
Submitting Verilog Programming Assignments10m
2 readings
Week 3 Readings1h 10m
Files for Week 3 Programming Assignments10m
2 practice exercises
Verilog Find the Errors20m
Module 3 Quiz30m
10 hours to complete
Verilog and System Verilog Design Techniques
In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.
10 hours to complete
10 videos (Total 48 min), 2 readings, 6 quizzes
10 videos
Combinatorial Circuits5m
Synchronous Logic: Latches and Flip Flops3m
Synchronous Logic: Counters and Registers5m
Buses and Tristate Buffers3m
Modular Design in Verilog3m
Testbenches in Verilog7m
Testbenches in Verilog II2m
Memory with Verilog4m
Verilog Finite State Machines7m
2 readings
Week 4 Readings15m
Files for Week 4 Programming Assignments10m
1 practice exercise
Module 4 Quiz30m
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