This course is part of the FPGA Design for Embedded Systems Specialization

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Part of the Master of Science in Electrical Engineering degree
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FPGA Design for Embedded Systems SpecializationUniversity of Colorado Boulder

About this Course

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This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design.   It uses natural learning processes to make learning the languages easy.  Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs.  Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained.  After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.

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Shareable Certificate

Earn a Certificate upon completion

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Course 2 of 4 in the

FPGA Design for Embedded Systems Specialization

Intermediate Level

Approx. 36 hours to complete

English

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Skills you will gain

Writing Code in Verilog
Simulating FPGA Designs
Designing FPGA Logic
Designing Test Benches
Writing code in VHDL

Flexible deadlines

Reset deadlines in accordance to your schedule.

Shareable Certificate

Earn a Certificate upon completion

100% online

Start instantly and learn at your own schedule.

Course 2 of 4 in the

FPGA Design for Embedded Systems Specialization

Intermediate Level

Approx. 36 hours to complete

English

Could your company benefit from training employees on in-demand skills?

Try Coursera for Business

Instructors

Instructor rating

4.25/5 (196 Ratings)

Timothy Scherr

Senior Instructor and Professor of Engineering Practice

Electrical, Computer, and Energy Engineering

83,445 Learners

5 Courses

Benjamin Spriggs

Lecturer and Scholar of Engineering Practice

Electrical, Computer, and Energy Engineering

27,704 Learners

1 Course

Offered by

University of Colorado Boulder

Start working towards your Master's degree

This course is part of the 100% online Master of Science in Electrical Engineering from University of Colorado Boulder. If you are admitted to the full program, your courses count towards your degree learning.

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Syllabus - What you will learn from this course

Content Rating82%(1,425 ratings)

Week1

Week 1

8 hours to complete

Basics of VHDL

This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.

8 hours to complete

10 videos (Total 48 min), 3 readings, 6 quizzes

10 videos

Introduction to Hardware Description Languages for FPGA Design4mWhy Learn VHDL?1mFPGA Design Flow3mIntro to VHDL: Finite State Machine3mHow to speak VHDL, first phrases6mVHDL Assignments, Operators, Types3mVHDL Rules and Syntax, Interface Ports3mVHDL in ModelSim: Download and Install3mVHDL in ModelSim: Adding to your Toolkit6mSubmitting VHDL Programming Assignments11m

3 readings

Hardware Description Languages for FPGA Design Assessment Strategy10mMisson 2-001: Week 1 Readings2hFiles for Week 1 Programming Assignments10m

2 practice exercises

VHDL Find the Code Errors30mModule 1 Quiz30m

Week2

Week 2

12 hours to complete

VHDL Logic Design Techniques

In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.

12 hours to complete

10 videos (Total 52 min), 2 readings, 6 quizzes

10 videos

Learning to speak VHDL (Intro)1mCombinatorial Circuits4mSynchronous Logic: Latches and Flip Flops4mSynchronous Logic: Counters and Registers6mBuses and Tristate Buffers3mModular Designs: Components, Generate and Loops in VHDL3mTest Benches in VHDL: Combinatorial8mTest Benches in VHDL: Synchronous5mMemory in VHDL7mFinite State Machines in VHDL8m

2 readings

Week 2 Readings2hFiles for Week 2 Programming Assignments10m

1 practice exercise

Module 2 Quiz30m

Week3

Week 3

7 hours to complete

Basics of Verilog

This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.

7 hours to complete

9 videos (Total 92 min), 2 readings, 6 quizzes

9 videos

Verilog for fun and profit (intro)3mYour First Verilog phrase11mVerilog Rules and Syntax; Keywords and Identifiers; Sigasi/Quartus editing12mVerilog Statements and Operators16mVerilog Modules, Port Modes and Data Types10mVerilog Structure10mTesting with ModelSim5mVerilog Evaluation11mSubmitting Verilog Programming Assignments10m

2 readings

Week 3 Readings1h 10mFiles for Week 3 Programming Assignments10m

2 practice exercises

Verilog Find the Errors20mModule 3 Quiz30m

Week4

Week 4

10 hours to complete

Verilog and System Verilog Design Techniques

In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.

10 hours to complete

10 videos (Total 48 min), 2 readings, 6 quizzes

10 videos

Learning to speak Verilog (intro)3mCombinatorial Circuits5mSynchronous Logic: Latches and Flip Flops3mSynchronous Logic: Counters and Registers5mBuses and Tristate Buffers3mModular Design in Verilog3mTestbenches in Verilog7mTestbenches in Verilog II2mMemory with Verilog4mVerilog Finite State Machines7m

2 readings

Week 4 Readings15mFiles for Week 4 Programming Assignments10m

1 practice exercise

Module 4 Quiz30m

Reviews

4.4

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TOP REVIEWS FROM HARDWARE DESCRIPTION LANGUAGES FOR FPGA DESIGN

by MSMay 15, 2020

This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.

by SSFeb 2, 2023

Excellent course, helped me to gain reasonably good foundation on both VHDL and Verilog effectively in a short period of time.

by SNJul 7, 2020

Though the support of this course is quite poor and the forum is really dull, the course in itself is really something!!

by JVFeb 23, 2021

Professors were top-notch and clearly explained the pros and cons of each of the languages. I hope I could meet them in person.

View all reviews

About the FPGA Design for Embedded Systems Specialization

The objective of this course is to acquire proficiency with Field Programmable Gate Arrays (FPGA)s for the purpose of creating prototypes or products for a variety of applications. Although FPGA design can be a complex topic, we will introduce it so that, with a little bit of effort, the basic concepts will be easily learned, while also providing a challenge for the more experienced designer. We will explore complexities, capabilities and trends of Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD). Conception, design, implementation, and debugging skills will be practiced. We will learn specifics around embedded IP and processor cores, including tradeoffs between implementing versus acquiring IP. Projects will involve the latest software and FPGA development tools and hardware platforms to help develop a broad perspective of the capabilities of various Programmable SoC solutions. Topics include:

Verilog, VHDL, and RTL design for FPGA and CPLD architectures FPGA development tools flow: specify, synthesize, simulate, compile, program and debug Configurable embedded processors and embedded software Use of soft-core and hard-core processors and OS options FPGA System engineering, software-hardware integration, and testing IP development and incorporating 3rd-party IP The capstone course will give the learner the opportunity to practice and implement the concepts covered by building FPGA systems based on low cost evaluation boards.

Frequently Asked Questions

When will I have access to the lectures and assignments?
Access to lectures and assignments depends on your type of enrollment. If you take a course in audit mode, you will be able to see most course materials for free. To access graded assignments and to earn a Certificate, you will need to purchase the Certificate experience, during or after your audit. If you don't see the audit option:
The course may not offer an audit option. You can try a Free Trial instead, or apply for Financial Aid.
The course may offer 'Full Course, No Certificate' instead. This option lets you see all course materials, submit required assessments, and get a final grade. This also means that you will not be able to purchase a Certificate experience.
What will I get if I subscribe to this Specialization?
When you enroll in the course, you get access to all of the courses in the Specialization, and you earn a certificate when you complete the work. Your electronic Certificate will be added to your Accomplishments page - from there, you can print your Certificate or add it to your LinkedIn profile. If you only want to read and view the course content, you can audit the course for free.
What is the refund policy?
If you subscribed, you get a 7-day free trial during which you can cancel at no penalty. After that, we don’t give refunds, but you can cancel your subscription at any time. See our full refund policy.
Is financial aid available?
Yes. In select learning programs, you can apply for financial aid or a scholarship if you can’t afford the enrollment fee. If fin aid or scholarship is available for your learning program selection, you’ll find a link to apply on the description page.

More questions? Visit the Learner Help Center.

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Hardware Description Languages for FPGA Design

About this Course

Skills you will gain