About this Course

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Flexible deadlines
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Intermediate Level
Approx. 36 hours to complete
English

Skills you will gain

Writing Code in VerilogSimulating FPGA DesignsDesigning FPGA LogicDesigning Test BenchesWriting code in VHDL
Shareable Certificate
Earn a Certificate upon completion
100% online
Start instantly and learn at your own schedule.
Flexible deadlines
Reset deadlines in accordance to your schedule.
Intermediate Level
Approx. 36 hours to complete
English

Offered by

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University of Colorado Boulder

Start working towards your Master's degree

This course is part of the 100% online Master of Science in Electrical Engineering from University of Colorado Boulder. If you are admitted to the full program, your courses count towards your degree learning.

Syllabus - What you will learn from this course

Week
1

Week 1

8 hours to complete

Basics of VHDL

8 hours to complete
10 videos (Total 48 min), 2 readings, 6 quizzes
10 videos
Why Learn VHDL?1m
FPGA Design Flow3m
Intro to VHDL: Finite State Machine3m
How to speak VHDL, first phrases6m
VHDL Assignments, Operators, Types3m
VHDL Rules and Syntax, Interface Ports3m
VHDL in ModelSim: Download and Install3m
VHDL in ModelSim: Adding to your Toolkit6m
Submitting VHDL Programming Assignments11m
2 readings
Misson 2-001: Week 1 Readings2h
Files for Week 1 Programming Assignments10m
2 practice exercises
VHDL Find the Code Errors30m
Module 1 Quiz30m
Week
2

Week 2

12 hours to complete

VHDL Logic Design Techniques

12 hours to complete
10 videos (Total 52 min), 2 readings, 6 quizzes
10 videos
Combinatorial Circuits4m
Synchronous Logic: Latches and Flip Flops4m
Synchronous Logic: Counters and Registers6m
Buses and Tristate Buffers3m
Modular Designs: Components, Generate and Loops in VHDL3m
Test Benches in VHDL: Combinatorial8m
Test Benches in VHDL: Synchronous5m
Memory in VHDL7m
Finite State Machines in VHDL8m
2 readings
Week 2 Readings2h
Files for Week 2 Programming Assignments10m
1 practice exercise
Module 2 Quiz30m
Week
3

Week 3

7 hours to complete

Basics of Verilog

7 hours to complete
9 videos (Total 92 min), 2 readings, 6 quizzes
9 videos
Your First Verilog phrase11m
Verilog Rules and Syntax; Keywords and Identifiers; Sigasi/Quartus editing12m
Verilog Statements and Operators16m
Verilog Modules, Port Modes and Data Types10m
Verilog Structure10m
Testing with ModelSim5m
Verilog Evaluation11m
Submitting Verilog Programming Assignments10m
2 readings
Week 3 Readings1h 10m
Files for Week 3 Programming Assignments10m
2 practice exercises
Verilog Find the Errors20m
Module 3 Quiz30m
Week
4

Week 4

10 hours to complete

Verilog and System Verilog Design Techniques

10 hours to complete
10 videos (Total 48 min), 2 readings, 6 quizzes
10 videos
Combinatorial Circuits5m
Synchronous Logic: Latches and Flip Flops3m
Synchronous Logic: Counters and Registers5m
Buses and Tristate Buffers3m
Modular Design in Verilog3m
Testbenches in Verilog7m
Testbenches in Verilog II2m
Memory with Verilog4m
Verilog Finite State Machines7m
2 readings
Week 4 Readings15m
Files for Week 4 Programming Assignments10m
1 practice exercise
Module 4 Quiz30m

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About the FPGA Design for Embedded Systems Specialization

FPGA Design for Embedded Systems

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