Learner Reviews & Feedback for Hardware Description Languages for FPGA Design by University of Colorado Boulder
About the Course
Top reviews
I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .
This is very good course , but i found some little missing details related to reading materials .\n\nBut this was really very helpful course for me as fresher .
51 - 75 of 115 Reviews for Hardware Description Languages for FPGA Design
By Mahendra V
•Good Learning with structured assignments.
By himanshu g
•A Nice Course which required more hardwork
By Soorya K
•Assignment programs are very challenging.
By SAMUELJUDE S
•extremely short crisp and knowledgeable
By Apurba D
•Liked the programming assignments...
By patrick
•good mix between theory and practice
By Ehtesham A K
•Excellent Course for FPGA learners.
By Carlos M
•Excellent materials and exercises.
By P S
•Very well explained the concepts.
By Ashish S
•Good Study material for Beginner
By Kondapally M R
•very informative and practical
By Abdul A
•Really a great experience!!
By MAVURU H K
•this course is very nice.
By Vinayakumar B
•Very good for beginners
By Ovidiu S
•High Value Course !
By Rinson V
•Very good course
By Mucha. S r
•Awesome course
By Dr. J V S
•Excellent
By segu v n k
•very good
By Mohsen s
•thanks
By Sanjana A R
•
By Lalit B
•feeling satisfactory after successfully completing the course. the instructors were the expert of the topic and explained very well. some of the programming assignments require more clarifications and learning which i found missing in the videos. videos are not enough to complete those assignments.
i am very happy to have this certification and would love to be the part of more learning by the coursera.
By Samer A A
•The course gives a good overview for the HDL. However, the assignments templates needs to be revised because there were some errors. Also, the requirements sometimes are vague, there is no specific specifications like synchronous/asynchronous signals active high/low clock. But, overall it was good time to revise HDL. I am looking forward to be involved in more advanced courses related to the FPGAs.
By Sangeerth P
•The course content was worthier and good. But the assignments and the methodology of assessing the assignments were not rigorous. The questions were not clear and elaborate. Once I uploaded a wrong Verilog code but I got 10/10 for that assignment. I don't know how. The course content was really good. But the method of evaluating the assignment could be made better.
By pedram k
•A good combination of introduction to VHDL and Verilog. Cover essential topics for design and test implementation. There are rooms to improvement regarding the assignments description. Also, having the test benches encrypted is fine, but better to make it open source for students once they have get enough grades for that specific problem.
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