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Learner Reviews & Feedback for Hardware Description Languages for FPGA Design by University of Colorado Boulder

4.3
stars
356 ratings
96 reviews

About the Course

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....

Top reviews

KK
Jun 4, 2020

This is very good course , but i found some little missing details related to reading materials .\n\nBut this was really very helpful course for me as fresher .

JP
Oct 6, 2020

I think this is a good start in learning how to write VHDL and Verilog.\n\nI would like to see a next level course or recommendations for further writing code.

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51 - 75 of 97 Reviews for Hardware Description Languages for FPGA Design

By P S

Aug 6, 2020

Very well explained the concepts.

By Ashish S

Oct 1, 2020

Good Study material for Beginner

By Kondapally M R

Jun 24, 2020

very informative and practical

By Abdul A

Nov 27, 2020

Really a great experience!!

By MAVURU H K

Aug 31, 2020

this course is very nice.

By Vinayakumar R B

May 26, 2020

Very good for beginners

By Ovidiu S

Nov 17, 2020

High Value Course !

By Rinson V

Aug 17, 2020

Very good course

By Mucha. S r

Aug 27, 2020

Awesome course

By Dr. J V S

Nov 13, 2020

Excellent

By segu v n k

Oct 29, 2020

very good

By Lalit B

Mar 4, 2020

feeling satisfactory after successfully completing the course. the instructors were the expert of the topic and explained very well. some of the programming assignments require more clarifications and learning which i found missing in the videos. videos are not enough to complete those assignments.

i am very happy to have this certification and would love to be the part of more learning by the coursera.

By Samer A A

Jul 7, 2020

The course gives a good overview for the HDL. However, the assignments templates needs to be revised because there were some errors. Also, the requirements sometimes are vague, there is no specific specifications like synchronous/asynchronous signals active high/low clock. But, overall it was good time to revise HDL. I am looking forward to be involved in more advanced courses related to the FPGAs.

By SANGEERTH P

Jun 29, 2020

The course content was worthier and good. But the assignments and the methodology of assessing the assignments were not rigorous. The questions were not clear and elaborate. Once I uploaded a wrong Verilog code but I got 10/10 for that assignment. I don't know how. The course content was really good. But the method of evaluating the assignment could be made better.

By pedram k

Apr 21, 2020

A good combination of introduction to VHDL and Verilog. Cover essential topics for design and test implementation. There are rooms to improvement regarding the assignments description. Also, having the test benches encrypted is fine, but better to make it open source for students once they have get enough grades for that specific problem.

By SHIKHAR S

May 15, 2020

This course provides insights into the world of hardware design. The assignments provided were quite challenging and diverse. The Testbench files were provided on which the code had to be tested and simulation had to be done on ModelSim, provided by MentorGraphics.It was quite an interesting course.

By Borys I

Aug 29, 2020

Good training. Could be better. Students should pay attention that most of information they will learn not from video but from books recommended at the end of video. Practical work has abit cryptic task description. what exactly doing particular wire is not clear. U have to google a lot to find out.

By KUNAL M

May 17, 2020

Good for beginners.Though the instructors can improve upon how they present the concepts by incorporating few complex examples on both Verilog and VHDL.The assignments questions need to be different for both the languages.

By Timothy

Apr 30, 2020

I did love how explanations were made and especially the flexibility in the submission of quizzes and assignment. My understanding of VHDL and Verilog have been made batter. The instructors are top notch.

By DHANANJAY K P

May 16, 2020

This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.

By Rohit l

May 2, 2020

The Verilog course was very good.

However the vhdl course could have been better.Needed a bit more clarity on the assignments.The lectures could have used a bit more explanation.

By harsh

May 15, 2020

The Programming Assignments need to be more elaborate, things like reset is active low or active high and more details should be mentioned.

By Rishi J

Sep 4, 2020

The course is good. It will enhance your vhdl and verilog skills but there are some places where i found insufficient details.

By Aishwarya S

May 7, 2020

FIFO assignments in both Verilog and VHDL should define purpose of all the internal nets and registers listed in the problem.

By Raghul R

Jun 25, 2020

Teaching methodology requires a lot more improvement. Assignments are challenging and its nice to try.