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Learner Reviews & Feedback for Hardware Description Languages for FPGA Design by University of Colorado Boulder

4.3
stars
408 ratings
114 reviews

About the Course

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....

Top reviews

JS
Jun 6, 2021

I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .

KK
Jun 4, 2020

This is very good course , but i found some little missing details related to reading materials .\n\nBut this was really very helpful course for me as fresher .

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101 - 115 of 115 Reviews for Hardware Description Languages for FPGA Design

By V S V

Sep 29, 2020

Videos could be better, felt it was too fast and didn't cover the concepts well enough

By Harsh A

Jun 15, 2020

Verilog part is explained very well but VHDL part completely unsatisfied.

By Sachin A

Apr 21, 2020

Very introductory. Verilog and VHDL exercises are copied.

By Sakshat R

May 28, 2020

Innovative teaching, but very poor assignments

By Samuel C

Aug 14, 2020

A decent introduction to HDL.

By Pushkar A

Sep 30, 2020

Teaching could be better.

By JYOTI S S

Jul 11, 2021

good

By Damián E A

Mar 22, 2021

Weeks 3 and 4 are the same as weeks 1 and 2, just in another (very similar) language. No many new topics compared to the first course of the specialization. Several weeks assignment are blocked by very tricky quizzes that can be taken only once every 72 hours, what makes it very difficult to accomplish everything in only 4 weeks.

By Eddy Z

Feb 12, 2021

Instruction is somewhat unclear. The instructors just read through example code but fail to adequately explain how the Verilog and VHDL languages actually work. I learned most of that from a separate textbook. Homework assignments' instructions are often lacking in specificity, forcing students to make assumptions.

By Rishi D

Jun 12, 2020

teacher as well as way of teaching is not good . assignments are great though

By Ethan R

Apr 11, 2020

The highlight of this course was the recommended reading materials.

By Surabhi M

Nov 8, 2020

not clear.

By Han L L

Mar 19, 2021

THIS IS A SCAM!! Week2 Quiz failure resulting blocking on Readings page to get all the files you needed to do the rest of the assignment. And the quiz is only 1 attempt for 72 HOURS which means you will can't do anything for 3 days. And if you fail again, you will definitely miss the deadline!!

By saikumar s

Oct 31, 2020

There is no technical support

By Muhammet M K

Aug 23, 2021

awful