Traditionally, computing was classified into General-Purpose Computing performed by a General-Purpose Processor (GPP) and Application-Specific Computing performed by an Application-Specific Integrated Circuit (ASIC). As a trade-off between the two extreme characteristics of GPP and ASIC, reconfigurable computing has combined the advantages of both. On one hand reconfigurable computing can have better performance with respect to a software implementation but paying this in terms of time to implement. On the other hand a reconfigurable device can be used to design a system without requiring the same design time and complexity compared to a full custom solution but being beaten in terms of performance. The main advantage of a reconfigurable system is its high flexibility, while its main disadvantage is the lack of a standard computing model. In this module we are presenting a first definition of reconfigurable computing, describing the rationale behind it and introducing how this field has been influenced by the introduction of the FPGAs.

From the mid-1980s, reconfigurable computing has become a popular field due to the FPGA technology progress. An FPGA is a semiconductor device containing programmable logic components and programmable interconnects but no instruction fetch at run time, that is, FPGAs do not have a program counter. In most FPGAs, the logic components can be programmed to duplicate the functionality of basic logic gates or functional Intellectual Properties (IPs). FPGAs also include memory elements composed of simple flip-flops or more complex blocks of memories. Hence, FPGA has made possible the dynamic execution and configuration of both hardware and software on a single chip. This module provides a detailed description of FPGA technologies starting from a general description down to the discussion on the low-level configuration details of these devices, to the bitstream composition and the description of the configuration registers.

FPGA design tools must provide a design environment based on digital design concepts and components (gates, flip-flops, MUXs, etc.). They must hide the complexities of placement, routing and bitstream generation from the user. This module is not going through these steps in details, an entire course will be needed just for this, but it is important at least to have an idea of what it is happening behind the scene to better understand the complexity of the processes carried out by the tools you are going to use. Within this context, this module guides you through a simple example, which is abstracting the complexity of the underlying FPGA, starting from the description of the circuit you may be willing to implement to the bitstream used to configure the FPGA.

Before continuing in this terrific journey in the reconfigurable computing area, it can be useful to define a common language. Obviously, some of these terms have been already used but it is now time to better understand them and to make some order before continuing with more advanced concepts. Furthermore, as we know, FPGA configuration capabilities allow a great flexibility in hardware design and, as a consequence, they make it possible to create a vast number of different reconfigurable systems. These can vary from systems composed of custom boards with FPGAs, often connected to a standard PC or workstation, to standalone systems including reconfigurable logic and General Purpose Processors, to System-on-Chip's, completely implemented within a single FPGA mounted on a board, with only few physical components for I/O interfacing. There are different models of reconfiguration, and a scheme to classify them is presented in this module. We can consider this module as a transitional/turning point module. We have been exposed to some terminology and concepts and we are now ready to move forward. To do this, we need to combine all the pieces of the puzzles together and to invest a bit at looking at the overall picture, and this is exactly what this module has been designed for.

The reconfiguration capabilities of FPGAs give the designers extended flexibility in terms of hardware maintainability. FPGAs can change the hardware functionalities mapped on them by taking the application offline, downloading a new configuration on the FPGA (and possibly new software for the processor, if any) and rebooting the system. Reconfiguration in this case is a process independent of the execution of the application. A different approach is the one that considers reconfiguration of the FPGA as part of the application itself, giving it the capability of adapting the hardware configured on the chip resources according to the needs of a particular situation during the execution time. In this case we are referring to this reconfiguration as dynamic reconfiguration and the reconfiguration process is seen as part of the application execution, and not as a stage prior to it. This module illustrates a particular technique, which is extending the previous two, that has been viable for most recent FPGA devices, Partial Dynamic Reconfiguration. To fully understand what this technique is, the concepts of reconfigurable computing, static and dynamic reconfiguration, and the taxonomy of dynamic reconfiguration itself must be analyzed. In this way partial dynamic reconfiguration can be correctly placed in the set of system development techniques that it is possible to implement on a modern FPGA chip.

After presenting different solutions proposed to design and implement dynamic reconfigurable systems, this module will describe a general and complete design methodology that can be followed as a guideline for designing reconfigurable computing systems. To design and implement a reconfigurable computing system, designers need Computer-Aided Design (CAD) tools for system design and implementation, such as a design analysis tool for architecture design, a synthesis tool for hardware construction, a simulator for hardware behavior simulation, and a placement and routing tool for circuit layout. We may build these tools ourselves or we can also use commercial tools and platforms for reconfigurable system design. The first choice implies a considerable investment in terms of both time and effort to build a specific and optimized solution for the given problem, while the second one allows the re-use of knowledge, cores, and software to reach a good solution to the same problem more rapidly. This module is guiding the students through an historical view on how CAD frameworks evolved through the years. This is done to show how fast the technology is evolving and the rationale behind the choice made to improve the users experience when working with an FPGA-based system. Not only commercial tools are described, but also the personal journey done by the course instructor and his research team, starting from his early days as a PhD up to the research challenges they are nowadays working on.

We are working at the edge of the research in the area of reconfigurable computing. FPGA technologies are not used only as standalone solutions/platforms but are now included into cloud infrastructures. They are now used both to accelerate infrastructure/backend computations and exposed as-a-Service that can be used by anyone. Within this context we are facing the definition of new research opportunities and technologies improvements and the time cannot be better under this perspective. What it is needed now is new platform creation tools, monitoring and profiling infrastructure, better runtime management systems, static and dynamic workload partitioning, just to name a few possible areas of research. This module is concluding this course but posing interesting questions towards possible future research directions that may also point the students to other Coursera courses on FPGAs.