This course is part of the FPGA Design for Embedded Systems Specialization

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Timothy Scherr

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Part of the Master of Science in Electrical Engineering degree
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FPGA Design for Embedded Systems SpecializationUniversity of Colorado Boulder

About this Course

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This course will give you hands-on FPGA design experience that uses all the concepts and skills you have developed up to now.   You will need to purchase a DE10-Lite development kit.  You will setup and test the MAX10 DE10-Lite board using the FPGA design tool Quartus Prime and the System Builder.
You will:  
Design and test a Binary Coded Decimal Adder. 
Design and test a PWM Circuit, with verification by simulation. 
Design and test an ADC circuit, using Quartus Prime built-in tools to verify your circuit design. 
Create hardware for the NIOS II soft processor, including many interfaces, using Qsys (Platform Designer). Instantiate this design into a top-level DE10-Lite HDL file.
Compile your completed hardware using Quartus Prime.  
Enhance and test a working design, using most aspects of the Quartus Prime Design Flow and the NIOS II Software Build Tools (SBT) for Eclipse.
Create software for the NIOS II soft processor, including many interfaces, using Qsys (Platform Designer) and the SBT.
Compile your completed software using the SBT.
Use Quartus Prime to program both the FPGA hardware configuration and software code in you DE10-Lite development kit.  
Record all your observations in a lab notebook pdf. 
Submit your project files and lab notebook for grading.
This course consists of 4 modules, approximately 1 per week for 4 weeks.   Each module will include an hour or less of video lectures, plus reading assignments, discussion prompts, and project assignment that involves creating hardware and/or software in the FPGA.

Flexible deadlines

Reset deadlines in accordance to your schedule.

Shareable Certificate

Earn a Certificate upon completion

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Coursera Labs

Includes hands on learning projects.

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Course 4 of 4 in the

FPGA Design for Embedded Systems Specialization

Intermediate Level

You should have a experience in digital design and C programming before taking this course, and also complete the first 3 courses in this series.

Approx. 29 hours to complete

English

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What you will learn

Create a working FPGA design using Quartus Prime and run it on an evaluation board
Understand and practice all aspects of FPGA development, including conception, design, implementation, and debugging.
Create in the FPGA a working system on a chip design with Nios II soft processor, RAM and FLASH memory, and several peripherals.
Become familiar with the FGPA development flow, particularly in the case of a SoC with software development flow included.

Skills you will gain

Softcore Processor Design
Programmable Logic Design

Flexible deadlines

Reset deadlines in accordance to your schedule.

Shareable Certificate

Earn a Certificate upon completion

100% online

Start instantly and learn at your own schedule.

Coursera Labs

Includes hands on learning projects.

Learn more about Coursera Labs

Course 4 of 4 in the

FPGA Design for Embedded Systems Specialization

Intermediate Level

You should have a experience in digital design and C programming before taking this course, and also complete the first 3 courses in this series.

Approx. 29 hours to complete

English

Could your company benefit from training employees on in-demand skills?

Try Coursera for Business

Instructor

Instructor rating

4.75/5 (8 Ratings)

Timothy Scherr

Senior Instructor and Professor of Engineering Practice

Electrical, Computer, and Energy Engineering

83,818 Learners

5 Courses

Offered by

University of Colorado Boulder

Start working towards your Master's degree

This course is part of the 100% online Master of Science in Electrical Engineering from University of Colorado Boulder. If you are admitted to the full program, your courses count towards your degree learning.

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Syllabus - What you will learn from this course

Week1

Week 1

10 hours to complete

Hands on: Altera MAX10 Hardware Setup

In this module you will begin your hands-on exploration of FPGA design by setting up a target board, the DE10-Lite based on the MAX10 Intel Altera FPGA. In this module you will

10 hours to complete

5 videos (Total 15 min), 4 readings, 8 quizzes

Week2

Week 2

8 hours to complete

Develop a Mixed Signal System

The goal of this module is to develop a mixed-signal system. You will construct hardware that uses the Analog to Digital Converter (ADC) inputs and Pulse Width Modulate (PWM) outputs to make a voltage measuring instrument. In this module you will

 Create a working design, using most aspects of the Quartus Prime Design Flow.  Design and test a PWM Circuit, with verification by simulation.  Design and test an ADC circuit, using Quartus Prime built-in tools to verify your circuit design.  Record all your observations in a lab notebook pdf.  Submit your project files and lab notebook for grading. Completing this module will help prepare you for the work to be done in the modules that follow.

8 hours to complete

2 videos (Total 4 min), 1 reading, 4 quizzes

Week3

Week 3

8 hours to complete

Create a System on a Chip with NIOS II

The goal of this module is to develop the hardware for a System on a Chip (SoC). You will construct hardware that creates a NIOS II soft processor along with several interfaces to devices on the DE10-Lite development kit. In this module you will

 Create a working design, using most aspects of the Quartus Prime Design Flow.  Create hardware for the NIOS II soft processor, including many interfaces, using Qsys (Platform Builder). Instantiate this design into a top-level DE10-Lite HDL file.  Compile your completed hardware using Quartus Prime.  Record all your observations in a lab notebook.  Submit your project files and lab notebook for grading. Completing this module will provide a platform for the work to be done in the module that follows.

8 hours to complete

2 videos (Total 5 min), 1 reading, 3 quizzes

Week4

Week 4

5 hours to complete

Software for a System on a Chip

The goal of this module is to develop the software for a System on a Chip (SoC). You will build software for a NIOS II soft processor you built in Module 3, using several interfaces to devices on the DE10-Lite development kit as well. In this module you will

 Enhance and test a working design, using most aspects of the Quartus Prime Design Flow and the NIOS II Software Build Tools (SBT) for Eclipse.  Create software for the NIOS II soft processor, including many interfaces, using Qsys (Platform Builder) and the SBT.  Compile your completed software using the SBT.  Use Quartus Prime to program both the FPGA hardware configuration and software code in you DE10-Lite development kit. You will then test your new embedded system.  Record all your observations in a lab notebook pdf.  Submit your project files and lab notebook for grading. Completing this module will finish your work for this course.

5 hours to complete

2 videos (Total 5 min), 1 reading, 3 quizzes

Reviews

4.8

7 reviews

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TOP REVIEWS FROM FPGA CAPSTONE: BUILDING FPGA PROJECTS

by DKMay 28, 2021

Requires knowledge of FPGA design flow (make sure to take 3 courses before this one), great practical tasks that complete the whole specialization.

by OSJan 27, 2021

This specialization has a very good balance between deepness and breadth of transmitted knowledge. Thank you !

by CLJan 25, 2022

In general a good course structure and content. It lacks support on question and exercises.

View all reviews

About the FPGA Design for Embedded Systems Specialization

The objective of this course is to acquire proficiency with Field Programmable Gate Arrays (FPGA)s for the purpose of creating prototypes or products for a variety of applications. Although FPGA design can be a complex topic, we will introduce it so that, with a little bit of effort, the basic concepts will be easily learned, while also providing a challenge for the more experienced designer. We will explore complexities, capabilities and trends of Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD). Conception, design, implementation, and debugging skills will be practiced. We will learn specifics around embedded IP and processor cores, including tradeoffs between implementing versus acquiring IP. Projects will involve the latest software and FPGA development tools and hardware platforms to help develop a broad perspective of the capabilities of various Programmable SoC solutions. Topics include:

Verilog, VHDL, and RTL design for FPGA and CPLD architectures FPGA development tools flow: specify, synthesize, simulate, compile, program and debug Configurable embedded processors and embedded software Use of soft-core and hard-core processors and OS options FPGA System engineering, software-hardware integration, and testing IP development and incorporating 3rd-party IP The capstone course will give the learner the opportunity to practice and implement the concepts covered by building FPGA systems based on low cost evaluation boards.

Frequently Asked Questions

When will I have access to the lectures and assignments?
Access to lectures and assignments depends on your type of enrollment. If you take a course in audit mode, you will be able to see most course materials for free. To access graded assignments and to earn a Certificate, you will need to purchase the Certificate experience, during or after your audit. If you don't see the audit option:
The course may not offer an audit option. You can try a Free Trial instead, or apply for Financial Aid.
The course may offer 'Full Course, No Certificate' instead. This option lets you see all course materials, submit required assessments, and get a final grade. This also means that you will not be able to purchase a Certificate experience.
What will I get if I subscribe to this Specialization?
When you enroll in the course, you get access to all of the courses in the Specialization, and you earn a certificate when you complete the work. Your electronic Certificate will be added to your Accomplishments page - from there, you can print your Certificate or add it to your LinkedIn profile. If you only want to read and view the course content, you can audit the course for free.
Is financial aid available?
Yes. In select learning programs, you can apply for financial aid or a scholarship if you can’t afford the enrollment fee. If fin aid or scholarship is available for your learning program selection, you’ll find a link to apply on the description page.

More questions? Visit the Learner Help Center.

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FPGA Capstone: Building FPGA Projects

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