This course is confusing and not laid out in a way that is conducive to learning. I would be surprised to know what learning pedagogues the instructors tried to employ. This unfortunately is par for the course from my experience in the colorado university Electrical Engineering department. It is a classic case of "Im an engineer, being in my presence will impart knowledge on you. I don't have a lesson plan or even know what the scientific process of education entails"

This is a teach yourself course with numerous pages of reading but only one of the three books is provided.

In 5 minutes I found online resources for free with step by step examples, vhdl example code, pspice pin outs and testbenches to verify. FOR FREE!!!!!!!

luckily I am not seeking a piece of paper from CU BOULDER. I am seeking knowledge so I am going else where.

I wish I could give a higher rating, because it is an interesting course. But there are multiple issues with the content, presentation and assignments. I was assured by Coursera that the issues would be addressed by the course providers, but this has not happened.

So far this course isn't what I expected, very poor explained programming assignments. I'm currently at week 2 and the FIFO assignment and it is not explained very good.

Between the huge gaps in the information taught and the extremely faulty software provided, this course is far too difficult. And I ALREADY know one of the languages taught. I can't imagine trying to take this course as a beginner. References are made to textbooks that are never introduced, the submit system for programming assignments is ridiculous, and ModelSim does not even provide error feedback, which is crucial for a beginner. Dropping this course.

The content is taught well and the material is helpful to prepare for more intricate circuit designs. I am very satisfied with the guidance through both languages - VHDL and Verilog.

However, there is little guidance for the assignments, many of which are open for interpretation. Unfortunately, this leads to extrapolating the proper instructions through trial and error while investigating simulation results. The course needs to improve clarity for homework assignments.

There are a lot of unfixed issues with this course and the instructors are AWOL.

I think this is a good start in learning how to write VHDL and Verilog.

I would like to see a next level course or recommendations for further writing code.

Too simple, no real practice; vhdl and verilog assignments are exactly the same

I think this is a good start in learning how to write VHDL and Verilog.\n\nI would like to see a next level course or recommendations for further writing code.

I learned nothing

This is very good course , but i found some little missing details related to reading materials .

But this was really very helpful course for me as fresher .

The course helped in showing the different styles of the Verilog and VHDL coding.

Understood the advantages of Verilog and VHDL in real life applications

The course lectures are useful and explanatory. The reason why I deduct 2 stars is homework instructions are sometimes very vague, e.g. synchronous reset or not, instruction's variable name does not match the ones given in starter code. The homework starter code sometimes contain errors too. The makes writing the homework sometimes a guess work of whether the code should be implemented one way vs. another.

the course is arranged well but the teaching methodology is not good the teachers are just reading the ppts secondly assignments submission way is troublesome

Videos could be better, felt it was too fast and didn't cover the concepts well enough

TLDR: The course introduces FPGA design nicely and gives people who don't know where to start a nice path to follow. However, blatant errors and misleading information built into assignments, quizzes, and readings make for many headaches. Check the forums for help.

The good: This course is reasonably good at introducing FPGA concepts, terminology, and design methods to students who already have a superficial understanding of integrated circuits. It provides a nice path for those who don't know where to start when trying to learn FPGA. It also briefly goes into some of the more interesting features of FPGAs, without getting into textbook levels of detail. Most or all of the readings can be found free online.

The bad: Some of the programming assignments are unclear in the instructions, leaving out important details. They also contain misleading code at times. Why is a reset signal provided if it's never used in the simulation? Why do the instructions tell me to use an increment signal to increase a counter, but then the simulation holds these increment signals high the entire time? These kinds of bizarre discrepancies between instructions and what is actually happening make the assignments a huge pain at times. Quizzes can be equally confusing.

Some of the readings teach FPGA programming concepts but don't use proper syntax in their examples. The "Introduction to Verilog" text in particular has LOTS of errors.

Professor Scherr will step through the code in some slides and explain what it's doing, which is helpful. Professor Spriggs points to code in slides and doesn't tell you what's happening. If you're already very familiar with programming this might not be a big deal, but it left me with lots of questions and no answers.

Overall I would recommend this course as a starting point, but would suggest outside resources for further learning. If you're stuck on something, don't think about it too hard and just check the forums. Your issue could likely be a flaw in the assignment/quiz.

Instruction is somewhat unclear. The instructors just read through example code but fail to adequately explain how the Verilog and VHDL languages actually work. I learned most of that from a separate textbook. Homework assignments' instructions are often lacking in specificity, forcing students to make assumptions.

THIS IS A SCAM!! Week2 Quiz failure resulting blocking on Readings page to get all the files you needed to do the rest of the assignment. And the quiz is only 1 attempt for 72 HOURS which means you will can't do anything for 3 days. And if you fail again, you will definitely miss the deadline!!

This course is a waste of time. It is OK as an overview of vhdl/verilog but it is not by any means a university quality course. Not worth the price or your time.

I had the opportunity to learn both VHDL and Verilog in same course. And compare the constructs of these two HDLs. Thank you very much. Best Regards