This course provides insights into the world of hardware design. The assignments provided were quite challenging and diverse. The Testbench files were provided on which the code had to be tested and simulation had to be done on ModelSim, provided by MentorGraphics.It was quite an interesting course.

Good training. Could be better. Students should pay attention that most of information they will learn not from video but from books recommended at the end of video. Practical work has abit cryptic task description. what exactly doing particular wire is not clear. U have to google a lot to find out.

Its a good course that explain the fundamental operators and design methods to construct hardware system units. I only have a trouble with the last design in the week 2 and week 3, and it is that it lacks detail about the requirements of the problem.

Good for beginners.Though the instructors can improve upon how they present the concepts by incorporating few complex examples on both Verilog and VHDL.The assignments questions need to be different for both the languages.

I did love how explanations were made and especially the flexibility in the submission of quizzes and assignment. My understanding of VHDL and Verilog have been made batter. The instructors are top notch.

This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.

The Verilog course was very good.

However the vhdl course could have been better.Needed a bit more clarity on the assignments.The lectures could have used a bit more explanation.

Good VHDL intro, Verilog was kind of light, especially the reference material. Free Range VHDL was a great reference. The Verilog section needs something similar.

The content of the course is excellent, but the design of the asigments delay your progress, because if you fail a quiz you have to wait 72h to apply again.

The Programming Assignments need to be more elaborate, things like reset is active low or active high and more details should be mentioned.

The course is good. It will enhance your vhdl and verilog skills but there are some places where i found insufficient details.

FIFO assignments in both Verilog and VHDL should define purpose of all the internal nets and registers listed in the problem.

Siento que faltan mas ejemplos y practicas, y en cuanto al apartado de lenguaje Verilog falta explicar aun mas sintaxis

Teaching methodology requires a lot more improvement. Assignments are challenging and its nice to try.

this course is given good idea of Hardware Description Language and i understood the concepts well.

Course content is moderate. But also have complexity level higher for a beginner.

its a very nice course. Its help me a lot to understand the basic of fpga.

A very engaging course to do for beginners having fundamentals strong.

Explanations are not that good for some circuits like memory

There should have been more examples of problems.

a big thank you to all the professiors

Concise, practical and useful

It should be more elaborative

cours très intéressant

i love this course