IBM

Dataflow Architectures for AI Specialization

IBM

Dataflow Architectures for AI Specialization

Master Dataflow Architectures for AI.

Learn how dataflow accelerators execute, compile, move data, and achieve performance.

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Get in-depth knowledge of a subject
Intermediate level

Recommended experience

4 weeks to complete
at 8 hours a week
Flexible schedule
Learn at your own pace
Get in-depth knowledge of a subject
Intermediate level

Recommended experience

4 weeks to complete
at 8 hours a week
Flexible schedule
Learn at your own pace

What you'll learn

  • Understand how dataflow architectures execute AI workloads and how they differ from GPUs and other accelerators.

  • Trace AI workloads through PyTorch, compiler graphs, memory systems, and accelerator execution.

  • Profile, debug, and optimize AI workloads using compiler tools, performance analysis, and Roofline modeling.

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Taught in English
Recently updated!

October 2026

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Specialization - 6 course series

The Accelerator Landscape

The Accelerator Landscape

Course 1, 3 hours

What you'll learn

  • ·Explain why AI workloads benefit from domain-specific accelerators using Amdahl's law and arithmetic intensity.

  • ·Compare execution and memory models across GPU, TPU, Cerebras, Groq, and IBM Spyre.

  • ·Use a roofline model to distinguish compute-bound from memory-bound workloads.

Dataflow Execution Models

Dataflow Execution Models

Course 2, 5 hours

What you'll learn

  • ·Explain dataflow firing rules and the trade-offs of static and dynamic scheduling.

  • ·Trace a PyTorch model with torch.fx and annotate graph nodes with compute and memory cost.

  • ·Compare how TPU, Groq, Cerebras, and IBM Spyre implement dataflow execution.

Compilation for Dataflow

Compilation for Dataflow

Course 3, 5 hours

What you'll learn

  • Trace the PyTorch 2 compilation path from TorchDynamo through TorchInductor.

  • Find and fix graph breaks and diagnose recompilation in compiled models.

  • Compare fusion, tiling, layout, and scheduling decisions across Inductor, XLA, and Spyre.

Memory Systems in Dataflow Architectures

Memory Systems in Dataflow Architectures

Course 4, 5 hours

What you'll learn

  • Explain why low-batch decode is often bandwidth-bound and estimate its arithmetic intensity.

  • Compare caches, scratchpads, and on-chip SRAM across accelerator architectures.

  • Size the KV cache and evaluate serving techniques that reduce or manage its memory cost.

Debugging Across the Dataflow Stack

Debugging Across the Dataflow Stack

Course 5, 2 hours

What you'll learn

  • Locate failures in compiled AI workloads by compiler stage and software layer.

  • Distinguish numerical differences from logic bugs using high-precision references and tolerances.

  • Use ablation, provenance, logs, and comparison to narrow the first point of divergence.

Performance Modeling and Optimization

Performance Modeling and Optimization

Course 6, 2 hours

What you'll learn

  • Bound operation runtime from FLOPs and bytes and place workloads on a roofline.

  • Profile LLM decode and separate time dominated by compute, memory movement, and overhead.

  • Benchmark compiled inference correctly and tune serving shapes using measured evidence.

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Instructor

Kaoutar El Maghraoui
1 Course1 learner

Offered by

IBM

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