Semiconductor yield excursions demand rapid diagnosis. This course equips early-career data analysts and technicians with three core diagnostic capabilities: selecting the right electrical characterization method (I-V, C-V, continuity) for device-level failure symptoms; interpreting statistical process control (SPC) charts to distinguish random contamination from systematic process misalignment; and executing a five-step structured triage workflow to isolate root causes using data-driven reasoning and Pareto analysis. Through hands-on scenarios, learners develop the rigor and communication skills needed to serve as connectors between fab floor observations and process engineering decision-making.

By the end of this course, you will be able to: - Select an appropriate electrical characterization method (I-V, C-V, or continuity) to investigate a specified leakage or open-circuit symptom. - Interpret inline inspection charts to distinguish particle contamination from pattern misalignment anomalies. - Execute a structured triage workflow to narrow root cause of a yield excursion using provided pareto and binning data. Basic understanding of semiconductor device physics (PN junctions, MOSFETs, basic I-V characteristics); familiarity with statistical thinking (trends, anomalies, data patterns); experience reading technical charts and data visualizations. Wafer fab environment experience is helpful but not required.