As a hardware designer or a company, you want to protect your design intellectual property (IP) from being misused (by users, competitors, silicon foundry, etc). We will cover how you can build such protection during the design process which can be used as an evidence to support law enforcement protection. You are expected to understand the basic digital logic design knowledge covered in week 1. We will use several NP-hard problems as examples to illustrate the concepts of IP protection. These problems (graph vertex coloring problem and graph partitioning problem) will be introduced in the lecture and you do not need to know the concept of NP-complete.

This week you will learn the fundamentals about physical attacks: what are physical attacks, who are the attackers, what are their motivations, how can they attack your system (from hardware), what kind of skills/tools/equipment they should need to break your system, etc. You will also see what are the available countermeasures. You will learn how system security level and tamper resistance level are defined and some general guidelines on how to make your system secure by design. In the second part, you will learn a useful mathematical operation called modular exponentiation. It is widely used in modern cryptography but it is very computational expensive. You will see how security vulnerability might be introduced during the implementation of this operation and thus make the mathematically sound cryptographic primitives breakable. This will also be important for you to learn side channel attack next week.

This week, we focus on side channel attacks (SCA). We will study in-depth the following SCAs: cache attacks, power analysis, timing attacks, scan chain attacks. We will also learn the available countermeasures from software, hardware, and algorithm design.

This week we study hardware Trojan and trusted integrated circuit (IC) design. Hardware Trojans are additions or modifications of the circuit with malicious purposes. It has become one of the most dangerous and challenging threats for trusted ID design. We will give hardware Trojan taxonomies based on different criteria, explain how hardware Trojan work, and then talk about some of the existing approaches to detect them. We define trusted IC as circuit that does exactly what it is asked for, no less and no malicious more. We will illustrate this concept through the design space analysis and we will discuss several practical hardware Trojan prevention methods that can facilitate trust IC design.

This is the last week and we will cover some positive things on hardware security. We start with trust platform module (TPM), followed by physical unclonable functin (PUF), and FPGA-based system design. We conclude with a short discussion on the roles that hardware play in security and trust.