The write operation performed by type 1 and type 2 packets have the purpose

of writing to specific configuration registers.

The registers of a Xilinx FPGA can be found in the corresponding CONFIGURATION USER GUIDE

which is part of the public available documentation provided by Xilinx.

Each of these registers controls a particular feature of the device.

For the purpose of understanding the configuration process, some the relevant registers

are the CRC, IDCODE, FAR, and FDRI registers, just to name a few.

All the other registers are used for controlling aspects other than the configuration.

Again, for more details I love to invite to consult the documentation of the FPGA family of your interest.

The CYCLIC REDUNDANCY CHECK REGISTER, or CRC register for simplicity, is used to check

the correct transferring of the configuration data by storing the result

of a standard 16-bit checksum algorithm.

The bitstream has a pre-calculated checksum value at the end of configuration words

that is checked against the value calculated by the configuration logic.

If the two values don't match an error situation is created and the configuration process

must be repeated.

The CRC verification can be disabled for each family by setting the appropriate bit

of the Configuration Option Register, or COR... not really sure I am going to suggest you of doing it,

but you know, it is good to know that you may have this option.

To avoid the downloading of a bitstream created for the wrong device,

the IDCODE REGISTER must be written with a 32-bit word that is unique for every device.

This word is also hard-wired into the configuration logic, and the comparison of the contents of the register

with the hard-wired value can determine the correctness of the bitstream.

The FRAME ADDRESS REGISTER, or FAR, from now on, is where the position of the first configuration frame

is written, and it is thus important for knowing the physical location in partial bitstreams.

This register is automatically incremented by the FPGA's configuration logic

when the words that make up a configuration frame have been received in such a way

that only the first FAR value must be present in the bitstream file.

The frame address register is broken up into different fields,

depending on the specific FPGA family taken into consideration.

The Frame Address Register formats are defined, again, guess where?

In the configuration user guide.

It seems we do definitely have to get familiar with these documents

if we want to properly understand how our FPGAs are configured.

The terminology used in the manufacturer's user guides has been updated to be uniform across every family.

The BLOCK TYPE FIELD of the frame address register indicates broadly what kind of resources

the frame with that value will configure.

Different types are allowed: configuration of CLBs, IOBs, Interconnect and Block Special Frames,

Block RAM Content...and so on

The COLUMN ADDRESS field indicates what column of resources the frame is currently configuring.

Note, as you can also see from the figure, that a column is made of different frames.

Therefore, the MINOR ADDRESS field indicates a frame inside a particular CONFIGURATION COLUMN.

Sort of additional fields, introduced back in the days starting with the Virtex 4 devices,

have been introduced in the frame address register to address portions of configuration resources

other than entire vertical columns of the device array.

In particular, the TOP/BOTTOM BIT addresses the top or bottom half of the device

and the ROW ADDRESS is used to refer to a particular row of frames,

in the bottom or top half, depending on the chosen model.

The figure aggregates all the possible information that is contained in a generic FAR word,

either for the newest families and for older ones, like the Virtex II and Virtex II Pro FPGAs,

showing what is addressed in each field.

For the families that do not support a bi-dimensional granularity in configuration,

like the Virtex II Pro, only one row of columns must be considered in the figure,

while the whole addressing scheme, inclusive of the Row and Top/Bottom fields,

holds for the Virtex 4, 5, 6 and 7 series families.

It is true that Virtex II and Virtex II Pro are no longer supported, but as we know,

they have been quite important in the FPGAs history.

It is fair to consider them as the first devices used to bring Partial Dynamic Reconfiguration

to a general audience.

Therefore, it is was worthy to mention them also with respect to the topic

we are discussing right now.

The fields of the frame address register thus divide hierarchically the configuration memory space.

The top level component is a row of resources, addressed by the Top/Bottom bit

and by the Row Address, respectively.

The next level in the hierarchy is defined by the Column Address which defines

which column in a row is configured.

A frame within a column is then defined by its Minor Address and there is no way

to address configuration words within a single frame.

The atomic configuration unit in a Xilinx FPGA is thus represented by the frame,

as the addressing hierarchy clearly shows.

Finally the FRAME DATA REGISTER, INPUT REGISTER, or FDRI register, is used to write the words

that make up a frame.

The FPGA configuration logic implements the FDRI register as a shift register,

so that a frame is configured while the next one is being shifted in.

For this reason in the bitstream there is some padding data

in order to make the final writes to the configuration memory.

As previously stated, the FAR address is automatically incremented whenever a whole frame

has been written to the FDRI register.

The majority of a bitstream is thus made of the words that are written to the FDRI register.

Configuration Registers

FPGA computing systems: Background knowledge and introductory materials

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