In this presentation you use the RTL,

Technology Viewers and Chip Planner to analyze an FPGA design in Quartus Prime.

You use design files from the previous video,

compile design in Quartus Prime so that you

can follow along and perform each step along the way.

Feel free to pause the video as you enter commands into Quartus Prime.

Here's what we will cover in this video.

You will view a design at the RTL level,

view a design at the technology level,

analyze the design using the Chip Planner and

then analyze the design with the Power Play Power Analyzer.

Open Quartus Prime and open the pipemult project.

You should have the example of project files complete through compilation at this point.

Quartus Prime gives you a number of tools that can be

used to analyze the results of the design.

You should have a good idea of how your design should turn out but

sometimes the compiler will give you some unexpected results.

FPGA designers use the analysis tools to confirm the design result is what they expected.

One group of tools used for analysis are the viewers.

Under the tools menu click on netlist viewers.

You'll see that there are four different viewing tools available.

The RTL viewer, the technology map (post mapping) viewer,

the technology map (post fitting) viewer and the state machine viewer.

The netlist viewers are graphical tools that let you see

the results of synthesis and also place enroute.

You can also access them in the task window by expanding the analysis or filter sections.

The RTL viewer lets you view the design purely from

a logic design perspective and gives the simplest schematic representation of the design.

It can be used to verify your design entry and your logic.

The tool is available after analysis and elaboration.

From the tools menu select netlist viewers, RTL viewer.

The viewer displays the multiplier RAM and D flip flop

The input ports are on the left and the Q alpha port is on the right.

You can examine what components make up each of

the main blocks by expanding the netlist navigator

on the left pane.

You will see the listings of instances, primitives and ports.

If you click on the ports triangle,

it expands to show inputs and outputs.

Clicking on inputs expands all the input ports.

If you click on data it will expand to show each bit in the bus.

Click the ports triangle again to collapse this tree.

If you click on instances you'll see the multiplier and the RAM IP instances.

Keep clicking on the multiplier instance on each level until the entire tree is expanded.

You will see that the multiplier is made of

two atomic units that are primitives in the FPGA architecture.

Click on the instances triangle to collapse this tree.

Now in the schematic,

click on the plus sign in the upper right corner of the mult inst block.

This block will then expand to show the LPM under mult component.

Click on the plus sign to expand the component.

It expands again to show a primitive.

Click on the plus sign again to expand to the atomic pieces,

the mac_mult1 and the mac_out2 blocks.

This shows you the most basic level of the multiplier instance.

As you did this, the netlist navigator should have expanded as well.

Click the minus signs in the blocks until you have returned to the main RTL view.

Now click the plus sign in the upper right corner of the RAM block.

It shows three primitive blocks,

the synchronous RAM block itself and a read address register and output register.

Click the minus sign to return to the top level view.

On the upper menu, click file and then close to close the RTL viewer.

The technology map viewer post mapping lets you view the design after synthesis.

Back in the main Quartus Prime window from the tools menu,

select netlist viewers technology map viewer (post

mapping).

Now you see how the design has been mapped to the FPGA primitives

including every buffer for each input and output to a pin.

Obviously there's a lot more detail here.

However, you will find that the view of the multiplier and the RAM are very similar

to the RTL viewer except that each primitive is enumerated.

On the upper menu,

click file and then close to close the technology map viewer.

The technology map (post fitting) viewer lets you view the design after fitting.

Back in the main Quartus Prime window from the tools menu,

select netlist viewers, technology map viewer (post fitting).

Click the view menu,

zoom in to see the results.

Scroll down to the bottom.

Here you see the addition of the J tag in configuration interfaces.

The TMS, TDI, T clock and other signals.

There is even more detail on this view although it's not too

different from the others for this relatively simple design.

Close the viewer as before.

Since there are no state machines in this design,

the state machine viewer isn't very helpful,

so we will skip it for now.

Next let's look at the Chip Planner.

Click on the tools menu then the Chip Planner.

The Chip Planner provides a visual display of

device resources laid out as they are on the device.

It can be used for analysis to create a design

forward plan and to implement Engineering Change Orders or ECOs in your design.

Integration with other Quartus Prime tools allows you to locate

a particular design entered to

your timing path on the actual occasion on the target device.

You can use the Chip Planner in conjunction with the resource property editor to

change connections between resources and make post compilation changes.

This requires a detailed knowledge of the design or the device architecture.

Such changes are eliminated the next time the design is compiled,

so they are generally used for manual improvements or

fixes just prior to device programming.

In general I don't recommend the creation of post compilation changes.

Usually you can get it compiled to produce the results you want without time consuming

manual intervention as the routing algorithms are now very sophisticated.

Most of the time where we use the Chip Planner for analysis to

understand how the design has been placed and to look for the cause of timing issues.

The level of detail shown on the Chip Planner depends on

the current zoom level as well as the modes

selected in the layer settings tab in the upper right hand corner.

Zoom in by using control space,

zoom out with shift control space.

Generally the logic array blocks or LABs are colored blue,

the DSP blocks are a white column and their RAM blocks are a 10 column.

Towards the bottom of the display you will see

some blocks are darker in color than others.

The Chip Planner uses a gradient color scheme in which

the color becomes darker as the utilization of a resource increases.

You may see some darker blocks in the lower right corner.

If you zoom in until these blocks fill the screen,

the layout becomes more apparent.

Clicking on the individual blocks creates a circuit diagram picture and there are

no properties window on the right side of the screen.

Here we see a RAM block and then a LAB used as a register output.

The Chip Planner has two editing modes, assignment and ECL.

The assignment mode allows us to make changes

that are applied by the fitter during the next place enroute operation.

Typically these changes include pin assignments and location assignments.

You can make these assignments in

the location assignments window in the lower right hand corner.

The ECL mode allows us to make post compilation changes like

logic placement or routing that are not retained after the next compilation.

You can use the Chip Planner to examine fan-in and fan-out of specific device resources.

Click on the used RAM block.

You can see the fan-out by clicking on the generate fan-out icon on

the toolbar or by using the view menu and selecting generate fan-out.

The routes from the RAM block outputs now appear.

Zoom out until you see the pins that are the destinations for these outputs.

Click on the RAM block again to reselect it.

Now, clear these routes by using view, clear unselected connections.

Now generate fan-in route so the RAM with view generate fan-in connections.

You can zoom in or out to examine these more closely.

Click file and then close to close the Chip Planner.

The early power estimator or EPE is

a spreadsheet analysis tool that enables

early power estimation based on device and package selection,

resource utilization and operating conditions.

Although the models within the estimator are very accurate,

accurate results overall require estimates of

the device clock speeds and routing that are probably not perfect.

Later estimates post fitting using

actual routing and placement information in the Quartus Prime,

Power Play Power Analyzer will be considerably more accurate.

However, it's good to get an early estimate because

the circuit board power supply designer will

need this information in order to size the power supply.

PP is available from

www.altera.com/support/support-resources/operation-and-testing/power/pow-powerplay.html

as there's a wealth of information about altera's power play tools.

To download the EPE, find the max 10 listing

and click download under the spreadsheet tool column.

You may need to update your copy of Excel to work with this tool.

When you have downloaded the max 10 under epe.xls,

store it in the project directory.

Data for the EPE could be entered manually or imported from

a previous project or imported from a partially completed design.

This allows you to estimate your power budget for

every power supply voltage early in the design cycle before all design files are

complete and allows for quick analysis of

the effect design changes will have on the power consumption of your project.

To import the data on the project menu,

click generate Power Play early power estimator file which will create a file with a

design revision name early_.csv.

To import this data to the EPE,

open the EPE and click Import csv found at the middle of the main tab.

Browse to a Power Play EPE file generated from

the Quartus II software and click open.

If the file is imported,

click OK. Clicking OK acknowledges the import is complete.

Now you should see power consumption from the logic RAM,

DSP, IO and clock blocks in the middle of the screen.

The calculations used to reduce

these results are given in detail in the tabs at the bottom.

The default power consumption display is typical.

Before power supply design we like to look at maximum.

To get current estimates for each voltage you must select

a maximum for the power characteristics on the left.

Click on the cell and a down arrow appears, select maximum.

Then click on the box underneath the power rail configuration on

the right and select dual supply.

You will then see the current for the 1.2 and 2.5 volt rails.

Clicking on the select power regulator button below this,

takes us to another sheet where we can enter the power supply regulator input voltages.

In my case the clock is assumed to be

100 megahertz yielding a power consumption of 82.55 Milliwatts.

The clock frequency can be edited directly in each of

the tabs to explore the effects of different clock speeds.

Once you have completed a design you can use

the Quartus Prime Power Play Power Analyzer tool

to get a better estimate of the power consumption.

This tool is very easy to use requiring very little user input.

Under the processing menu in Quartus Prime select Power Play Power Analyzer tool.

The best estimation accuracy is achieved using

signal activity from gate level simulations.

However, if you don't have simulation output you can use vector list estimation.

To do this, scroll down the center Power Play Analyzer window and hit start.

After it runs you should see

the message Quartus Prime Power Play Power Analyzer was successful in the message window.

Just above that message,

it tells the total power estimate for the design,

in my case 53.4 Milliwatts.

This is a typical power consumption.

You can run the analyzer game with it set to maximum by

clicking on the cooling solution in temperature button or settings from

the assignment menu and then clicking on operating settings and

conditions and choosing maximum from the power characteristics pull down menu.

Then you should see something closer to 80 Milliwatts which can be

viewed in the Power Play Power Analyzer report summary.

In this video you have learned how to view an FPGA design using the RTL viewer,

how to view an FPGA design using the technology viewer,

how to analyze an FPGA design using the Chip Planner and how to

determine early Power estimates using the Power Play Power Analyzer.

8. View the RTL

Introduction to FPGA Design for Embedded Systems

Meet the Instructors