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University of Illinois at Urbana-Champaign

About this Course

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A modern VLSI chip has a zillion parts -- logic, control, memory, interconnect, etc. How do we design these complex chips? Answer: CAD software tools. Learn how to build thesA modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this first part of the course is on key Boolean logic representations that make it possible to synthesize, and to verify, the gate-level logic in these designs. This is the first step of the design chain, as we move from logic to layout. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: Computational Boolean algebra, logic verification, and logic synthesis (2-level and multi-level).
Recommended Background
Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Exposure to basic VLSI at an undergraduate level is nice -- but it’s not necessary. We will keep the course self-contained, but students with some VLSI will be able to skip some background material.e tools in this class.

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Suggested: 7 hours/week...

Subtitles: English

Logic GateComputer-Aided Design (CAD)Digital DesignBoolean Algebra

Start instantly and learn at your own schedule.

Reset deadlines in accordance to your schedule.

Suggested: 7 hours/week...

Subtitles: English

Week

1In this module you will become familiar with the course and our learning environment. The orientation will also help you obtain the technical skills required for the course....

1 video (Total 25 min), 2 readings, 5 quizzes

Syllabus10m

Tools For This Course5m

Demographics Survey5m

In this module, we will introduce advanced Boolean algebra math concepts that make it possible to take a "computational" approach to Boolean algebra. ...

6 videos (Total 91 min), 2 readings

Computational Boolean Algebra: Boolean Difference15m

Computational Boolean Algebra: Quantification Operators13m

Computational Boolean Algebra: Application to Logic Network Repair16m

Computational Boolean Algebra: Recursive Tautology9m

Computational Boolean Algebra: Recursive Tautology—URP Implementation20m

Week 1 Overview10m

Week 1 Assignments10m

Week

2Week 2 introduces two powerful and important representation techniques that allow us to do SERIOUS computational Boolean algebra, on industrial-scale designs....

7 videos (Total 135 min), 2 readings, 2 quizzes

BDD Basics, Part 216m

BDD Sharing17m

BDD Ordering28m

Satisfiability (SAT), Part 113m

Boolean Constraint Propagation (BCP) for SAT17m

Using SAT for Logic25m

Week 2 Overview10m

Week 2 Assignments10m

Problem Set #1s

Week

3In Week 3, we will move from "representing" things to "synthesizing" things. In this case, synthesis means "optimization", or maybe the word "minimization" is more familiar from hand work with Kmaps or Boolean algebra....

8 videos (Total 119 min), 2 readings, 1 quiz

2-Level Logic: The Reduce-Expand-Irredundant Optimization Loop13m

2-Level Logic: Details for One Step: Expand20m

Multilevel Logic and the Boolean Network Model13m

Multilevel Logic: Algebraic Model for Factoring14m

Multilevel Logic: Algebraic Division14m

Multilevel Logic: Role of Kernels and Co-Kernels in Factoring14m

Multilevel Logic: Finding the Kernels18m

Week 3 Overview10m

Week 3 Assignments10m

Problem Set #2s

Week

4You now know that to factor a multi-level network to reduce its complexity, you must look at the kernels and co-kernels. You know how to "get" these for any node. But -- what do you do with a big network to actually FIND the right common divisors? This is called EXTRACTION. We then look at a new opportunity to optimize multi-level logic: Don't Cares. In simple designs, we usually regard Don't Cares as "impossible inputs" -- things that just do not happen, so we can choose the value the hardware creates to minimize the logic....

8 videos (Total 123 min), 2 readings, 3 quizzes

Mulitlevel Logic and Divisor Extraction—Multiple Cube Case20m

Multilevel Logic and Divisor Extraction—Finding Prime Rectangles & Summary10m

Multilevel Logic—Implicit Don't Cares, Part 117m

Multilevel Logic—Implicit Don't Cares, Part 211m

Multilevel Logic—Satisfiability Don't Cares10m

Multilevel Logic—Controllability Don't Cares19m

Multilevel Logic—Observability Don't Cares17m

Week 4 Overview10m

Week 4 Assignments10m

Problem Set #3s

Auxiliary Quiz of Serious BDDs15m

The University of Illinois at Urbana-Champaign is a world leader in research, teaching and public engagement, distinguished by the breadth of its programs, broad academic excellence, and internationally renowned faculty and alumni. Illinois serves the world by creating knowledge, preparing students for lives of impact, and finding solutions to critical societal needs. ...

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