About this Course

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Flexible deadlines
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Intermediate Level
Approx. 18 hours to complete
Subtitles: English

Skills you will gain

Primality TestVerilogDigital DesignStatic Timing Analysis
Shareable Certificate
Earn a Certificate upon completion
100% online
Start instantly and learn at your own schedule.
Flexible deadlines
Reset deadlines in accordance to your schedule.
Intermediate Level
Approx. 18 hours to complete
Subtitles: English

Offered by

University of Colorado Boulder logo

University of Colorado Boulder

Start working towards your Master's degree

This course is part of the 100% online Master of Science in Electrical Engineering from University of Colorado Boulder. If you are admitted to the full program, your courses count towards your degree learning.

Syllabus - What you will learn from this course

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Week 1

4 hours to complete

What's this programmable logic stuff anyway? History and Architecture

4 hours to complete
9 videos (Total 46 min), 4 readings, 2 quizzes
9 videos
Course Overview6m
1. Welcome to the world of programmable logic and FPGA design1m
2. A Brief History of Programmable Logic9m
3. CPLD Architecture5m
4. LUTs and FPGA Architecture8m
5. LUTs for Logic Design2m
6. Designing Adders6m
7. Designing Multipliers3m
4 readings
About This Course10m
Hardware Requirements10m
Week 1 Suggested Readings1h 20m
Week 2 Assignment Instructions and Files10m
1 practice exercise
Mission 002: Week 1 Quiz30m

Week 2

4 hours to complete

FPGA Design Tool Flow; An Example Design

4 hours to complete
11 videos (Total 121 min), 1 reading, 3 quizzes
11 videos
2. Downloading Quartus Prime2m
3. Installing Quartus Prime2m
4. Introducing Quartus Prime11m
5. Create a design project in Quartus Prime7m
6. Create a design in Quartus Prime13m
7. Compile a Design17m
8. View the RTL16m
9. Timing Analysis with Time Quest I9m
10. Timing Analysis with Time Quest II16m
11. Simulate a design with ModelSim17m
1 reading
Week 2 Suggested Readings20m
2 practice exercises
Mission 003 : Practice Opportunity30m
Mission 005: Week 2 Quiz30m

Week 3

3 hours to complete

FPGA Architectures: SRAM, FLASH, and Anti-fuse

3 hours to complete
8 videos (Total 80 min), 2 readings, 1 quiz
8 videos
2. Xilinx CPLD Architecture7m
3. Xilinx Small FPGAs8m
4. Xilinx Large FPGAs11m
5. Altera CPLDs and Small FPGAs8m
6. Altera Large FPGAs9m
7. Microsemi Single-chip FPGA solutions14m
8. Lattice Single-Chip FPGA solutions14m
2 readings
Week 3 Suggested Readings1h 20m
Week 4 Assignment Instructions and Files10m
1 practice exercise
Mission 006: Week 3 Quiz30m

Week 4

6 hours to complete

Programmable logic design using schematic entry design tools

6 hours to complete
10 videos (Total 180 min), 1 reading, 2 quizzes
10 videos
2. Advanced Schematic Entry for FPGA Design- Drawing and Hierarchy26m
3. Improving Productivity with IP Blocks25m
4. Improving Timing with Pipelining18m
5. FPGA IO: Getting In and Getting Out8m
6. Pin Assignments: Making them Spot On!20m
7. Programming the FPGA10m
8. Becoming one with Q: Qsys System Design20m
9.a Becoming one with Q Part II: Qsys System Design Finishing Touches25m
9.b Becoming one with Q Part III: Qsys System Design Finishing Touches19m
1 reading
Week 4 Suggested Readings1h 10m
1 practice exercise
Mission 008: Week 4 Quiz30m



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